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US6388533B2
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Programmable ring oscillator
Assignee: Texas Instruments Inc
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Filing: 2000-12-19
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Granted: 2002-05-14
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Expires: 2020-12-19
Abstract
Abstract A controllable ring oscillator clock circuit includes a plurality of ring oscillator stages disposed in a linear chain. Each stage has a latch that determines if this stage is the last stage in the ring. In a propagate state of the latch the ring pulse is sent to the next stage. In a return state of the latch the ring pulse is returned to the prior stage. The latches are programmed like a shift register. A more command transfers the propagate state to the next stage. This increases the length of the delay line and thus decreases the oscillator frequency. A less command transfers the return state to the prior state, decreasing the ring delay and increasing the oscillator frequency. In the preferred embodiment the delay stages are deployed as even and odd pairs with only the even or the odd stages changed at one time. This enables a simple structure because the pairs operate like a master-slave flip-flop, that is the data can move only a single stage at a time.
Inventors
- 👤 Gary L. Swoboda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:03
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/3648; G06F11/3656
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
260 words
A ring oscillator clock circuit comprising: a plurality of ring oscillator stages disposed in a linear chain from a first ring oscillator stage to a last ring oscillator state, each ring oscillator stage including a propagate input, a propagate output, a return input, a return output; a latch storing either a first state or a second state, said latch having a true output and a complement output, a first AND gate having a first input connected to said propagate input, a second input connected to said true output of said latch and an output connected to said propagate output, a second AND gate having a first input connected to said propagate input, a second input connected to said complement output of said latch and an output, and a third AND gate having a first input connected to said return input, a second input connected to said output of said second AND gate and an output connected to said return output; an output stage connecting said return output of said first ring oscillator stage to said propagate input of said first ring oscillator stage to circulate a ring pulse, said output stage generating an oscillator clock signal; wherein said propagate input of a ring oscillator stage is connected to said propagate output of a prior ring oscillator state; wherein said return input of a ring oscillator stage is connected to said return output of a next ring oscillator state; wherein said propagate output of said last ring oscillator stage is connected to said return input of said last ring oscillator stage.
Claim 2
Dependent Claim
260 words
A ring oscillator clock circuit comprising: a plurality of ring oscillator stages disposed in a linear chain from a first ring oscillator stage to a last ring oscillator state, each ring oscillator stage including a propagate input, a propagate output, a return input, a return output; a latch storing either a first state or a second state, said latch having a true output and a complement output, a first AND gate having a first input connected to said propagate input, a second input connected to said true output of said latch and an output connected to said propagate output, a second AND gate having a first input connected to said propagate input, a second input connected to said complement output of said latch and an output, and a third AND gate having a first input connected to said return input, a second input connected to said output of said second AND gate and an output connected to said return output; an output stage connecting said return output of said first ring oscillator stage to said propagate input of said first ring oscillator stage to circulate a ring pulse, said output stage generating an oscillator clock signal; wherein said propagate input of a ring oscillator stage is connected to said propagate output of a prior ring oscillator state; wherein said return input of a ring oscillator stage is connected to said return output of a next ring oscillator state; wherein said propagate output of said last ring oscillator stage is connected to said return input of said last ring oscillator stage.
Claim 3
Dependent Claim
252 words
The ring oscillator clock circuit of claim 1 , further comprising: a more delay line; a less delay line; and each ring oscillator stage wherein said latch includes a first latch AND gate having a first input, a second input and an output, said output of said first latch AND being said true output of said latch, and a second latch AND having a first input connected to said output of said first latch AND, a second input and an output connected to said first input of said first latch AND gate, said output being said complement output of said latch; each ring oscillator state further including a go input, a go output connected to said true output of said latch, a stop input, a stop output connected to said complement output of said latch; a first control AND gate having a first input connected to said go input, a second input connected to said more delay line and an output connected to said second input of said first latch AND gate, a second control AND gate having a first input connected to said stop input, a second input connected to said less delay line and an output connected to said second input of said second latch AND gate; wherein said go input of a ring oscillator stage is connected to said go output of a prior ring oscillator state; and wherein said stop input of a ring oscillator stage is connected to said stop output of a next ring oscillator state.
Claim 4
Dependent Claim
77 words
The ring oscillator clock circuit of claim 2 , wherein: said ring oscillator stages are denoted as alternate even ring oscillator stage and odd oscillator stage; said more line includes an even more line connected to even ring oscillator stages and an odd more line connected to odd ring oscillator states; and said less line includes an even less line connected to even ring oscillator stages and an odd less line connected to odd ring oscillator states.
Claim 5
Dependent Claim
121 words
The ring oscillator clock circuit of claim 3 , further comprising: a reference clock input for receiving a reference clock signal; a comparison circuit connected to said output state for receiving said oscillator clock signal, said reference clock input for receiving said reference clock signal, said comparison circuit generating alternating more even signals on said more even line and more odd signals on said more odd line if said oscillator clock signal has a frequency greater than a frequency of said reference clock signal, and generating alternating loss even signals on said loss even line and less odd signals on said less odd line if said oscillator clock signal has a frequency less than a frequency of said reference clock signal.
Claim 6
Dependent Claim
77 words
The ring oscillator clock circuit of claim 3 , further comprising: at least one clock control register; a pre-scalar circuit connected to at least one of said reference clock signal and said oscillator clock signal dividing at least one of said reference clock signal and said oscillator clock signal; and wherein said comparison circuit is connected to pre-scalar circuit for receiving said at least one of said divided reference clock signal and said divided oscillator clock signal.
Claim 7
Dependent Claim
61 words
The ring oscillator circuit of claim 5 , wherein: said clock control register includes a reference field storing a reference clock scaling factor and an oscillator field storing an oscillator clock scaling factor; said pre-scalar circuit divides said reference clock signal corresponding to said reference clock scaling factor and divides said oscillator clock signal corresponding to said oscillator clock scaling factor.
Claim 8
Dependent Claim
24 words
The ring oscillator circuit of claim 5 , wherein: said at least one clock control register is directly writable via an externally accessible bus.
Claim 9
Dependent Claim
36 words
The ring oscillator circuit of claim 5 , wherein: said at least one externally writable clock control register is indirectly writable via writing to an indirect access resister which is writable via an externally accessible bus.
Claim 10
Dependent Claim
25 words
The ring oscillator circuit of claim 5 , wherein: said at least one externally writable clock control register is writable via a serial scan chain.
Claim 11
Dependent Claim
168 words
The ring oscillator circuit of claim 5 , wherein: said clock control register includes a fixed delay number field storing an indication of a number of fixed delays; said output circuit further includes a plurality of fixed delay elements disposed in a chain from a first fixed delay element to a last fixed delay element, each fixed delay element having an input and an output, said input of said first fixed delay element connected to said return output of said first ring oscillator stage, said input of each fixed delay elements other than said first fixed delay element connected to said output of a prior fixed delay element, and a multiplexer having a plurality of inputs, each input connected to said output of a corresponding fixed delay element, a control input connected to said clock oscillator control register and an output connected to said propagate input of said first delay stage, said multiplexer selecting for output an input corresponding to said indication of said fixed delay number field.
Claim 12
Dependent Claim
53 words
The ring oscillator circuit of claim 1 , wherein: said output stage includes a glitch filter having an input connected to said return output of said first delay state and an output connected to said propagate input of said first delay stage, said glitch filter rejecting ring pulses less than a predetermined length.
References Cited (Backward Citations)
US5789985A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-05-13 | 2005-11-12 | 2006-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-13 | 2009-11-12 | 2010-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-05-13 | 2013-11-12 | 2014-05-14 | $7700.00 | Window Closed / Lapsed |