Patent US2877109A successfully refreshed from Google Patents.
Patent US6388320B2 successfully refreshed from Google Patents.
US6388320B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertically integrated semiconductor configuration
Assignee: Infineon Technologies AG
•
Filing: 2001-07-02
•
Granted: 2002-05-14
•
Expires: 2021-07-02
Abstract
Abstract A semiconductor configuration includes at least one semiconductor chip having a first chip side, a second chip side, and connections passing through the at least one semiconductor chip, active structures on the first chip side and the second chip side, the connections electrically connecting the active structures to one another, a support having a first support side, a second support side, plated-through holes, and non-conducting regions running alternately with regular spacings from the first support side to the second support side, the plated-through holes spaced apart from one another to define a hole spacing distance between the holes, contact connections connecting the second chip side to the first support side, the contact connections spaced apart from one another to define a connection spacing distance between the contact connections, and the hole spacing distance being smaller than the connection spacing distance.
Inventors
- 👤 Michael Smola
- 👤 Andreas Kux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:51
CPC Classifications
H; H10; H10W; H10W90/00; H10W20/00; H10W20/20; H10W90/20; H10W90/22; H10W90/297; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
147 words
A semiconductor configuration, comprising: at least one semiconductor chip having a first chip side, a second chip side, and connections passing through said at least one semiconductor chip; active structures on said first chip side and said second chip side, said connections electrically connecting said active structures to one another; a support having a first support side, a second support side, plated-through holes, and non-conducting regions running alternately with regular spacings from said first support side to said second support side, said plated-through holes spaced apart from one another to define a hole spacing distance between respective ones of said plated-through holes; contact connections connecting said second chip side to said first support side, said contact connections spaced apart from one another to define a connection spacing distance between respective ones of said contact connections; and said hole spacing distance being smaller than said connection spacing distance.
Claim 2
Dependent Claim
147 words
A semiconductor configuration, comprising: at least one semiconductor chip having a first chip side, a second chip side, and connections passing through said at least one semiconductor chip; active structures on said first chip side and said second chip side, said connections electrically connecting said active structures to one another; a support having a first support side, a second support side, plated-through holes, and non-conducting regions running alternately with regular spacings from said first support side to said second support side, said plated-through holes spaced apart from one another to define a hole spacing distance between respective ones of said plated-through holes; contact connections connecting said second chip side to said first support side, said contact connections spaced apart from one another to define a connection spacing distance between respective ones of said contact connections; and said hole spacing distance being smaller than said connection spacing distance.
Claim 3
Dependent Claim
67 words
The semiconductor configuration according to claim 1 , wherein said second support side is opposite said first support side, and at least one further semiconductor chip has: a first further chip side; a second further chip side; and active structures on said first further chip side and said second further chip side; and said at least one further semiconductor chip is disposed on said second support side.
Claim 4
Dependent Claim
44 words
The semiconductor configuration according to claim 1 , wherein said support has contact connections on at least one of said first support side and said second support side; said active structures have structure contacts; and said contact connections are connected to said structure contacts.
Claim 5
Dependent Claim
44 words
The semiconductor configuration according to claim 2 , wherein said support has contact connections on at least one of said first support side and said second support side; said active structures have structure contacts; and said contact connections are connected to said structure contacts.
Claim 6
Dependent Claim
14 words
The semiconductor configuration according claim 1 , wherein said support has passive connecting structures.
Claim 7
Dependent Claim
62 words
The semiconductor configuration according to claim 3 , wherein at least one of: said contact connections on said first support side are connected to one another; said contact connections on said second support side are connected to one another; and said contact connections on said first support side and said second support side are connected to one another through said plated-through holes.
Claim 8
Dependent Claim
62 words
The semiconductor configuration according to claim 4 , wherein at least one of: said contact connections on said first support side are connected to one another; said contact connections on said second support side are connected to one another; and said contact connections on said first support side and said second support side are connected to one another through said plated-through holes.
Claim 9
Dependent Claim
32 words
The semiconductor configuration according to claim 2 , wherein said support has plated-through holes and non-conducting regions running alternately with regular spacings from said first support side to said second support side.
Claim 10
Dependent Claim
32 words
The semiconductor configuration according to claim 3 , wherein said support has plated-through holes and non-conducting regions running alternately with regular spacings from said first support side to said second support side.
Claim 11
Dependent Claim
32 words
The semiconductor configuration according to claim 4 , wherein said support has plated-through holes and non-conducting regions running alternately with regular spacings from said first support side to said second support side.
Claim 12
Dependent Claim
32 words
The semiconductor configuration according to claim 5 , wherein said support has plated-through holes and non-conducting regions running alternately with regular spacings from said first support side to said second support side.
Claim 13
Dependent Claim
32 words
The semiconductor configuration according to claim 6 , wherein said support has plated-through holes and non-conducting regions running alternately with regular spacings from said first support side to said second support side.
Claim 14
Dependent Claim
32 words
The semiconductor configuration according to claim 7 , wherein said support has plated-through holes and non-conducting regions running alternately with regular spacings from said first support side to said second support side.
Claim 15
Dependent Claim
15 words
The semiconductor configuration according to claim 1 , wherein said support is a semiconductor wafer.
References Cited (Backward Citations)
EP0238089A2
Cited
US4774632A
Cited
US5382827A
Cited
US5793105A
Cited
US5825080A
Cited
EP0827203A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-05-13 | 2005-11-12 | 2006-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-13 | 2009-11-12 | 2010-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-05-13 | 2013-11-12 | 2014-05-14 | $7700.00 | Window Closed / Lapsed |