Sync signal generating circuit provided in semiconductor integrated circuit

Claim 2

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a variable delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit and delivering a delayed output; a first voltage generating circuit, connected to the variable delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the variable delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages and outputting an internal clock signal; an internal circuit connected to the voltage comparing circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a second delay circuit, connected to the voltage comparing circuit, for delaying the internal clock signal by a second time period that is substantially equal to said first time period, and delivering a delayed output; and a phase comparator, connected to the second delay circuit and the input buffer circuit, for comparing phases of outputs of the second delay circuit and the input buffer circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs, wherein a delay time in said variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

Claim 3

The sync signal generating circuit according to claim 1 , wherein said first time period in the first delay circuit is substantially equal to a sum of a signal delay time of the input buffer circuit relative to the external clock signal and a signal delay time of the internal circuit relative to the internal clock signal.

Claim 4

The sync signal generating circuit according to claim 1 , wherein said variable delay circuit comprises: a charge pump circuit for receiving the control signal and outputting a DC voltage corresponding to the control signal; and a third delay circuit having a power supply node and supplied with the DC voltage output from the charge pump circuit.

Claim 5

The sync signal generating circuit according to claim 3 , wherein said third delay circuit has tandem-connected inverters.

Claim 6

The sync signal generating circuit according to claim 2 , wherein said variable delay circuit comprises: a charge pump circuit for receiving the control signal and outputting a DC voltage corresponding to the control signal; a multiple stages of tandem-connected delay circuits; and a current-limiting element inserted between each of the delay circuits and a power supply node and controlled to have a turn-on resistance varying on the basis of the DC voltage output from the charge pump circuit.

Claim 7

The sync signal generating circuit according to claim 5 , wherein each of said delay circuits is a CMOS inverter circuit.

Claim 8

The sync signal generating circuit according to claim 2 , wherein said variable delay circuit comprises: a third delay circuit connected to the first delay circuit; a counter circuit, connected to the phase comparator, for counting the control signal; and a delay control circuit, connected to the counter circuit and the third delay circuit, for controlling the third delay circuit in accordance with the output of the counter circuit.

Claim 9

The sync signal generating circuit according to claim 7 , wherein said third delay circuit comprises tandem-connected inverters, and said delay control circuit comprises a selector circuit for selecting different outputs of the inverters of the third delay circuit and delivering the selected outputs.

Claim 10

The sync signal generating circuit according to claim 1 , further comprising a control signal output controller circuit, connected to the phase comparator and the variable delay circuit, for supplying the control signal from the phase comparator to the variable delay circuit at a predetermined timing.

Claim 11

The sync signal generating circuit according to claim 9 , wherein said control signal output controller circuit comprises: a frequency-division circuit, connected to the first delay circuit, for frequency-dividing the external clock signal; and a logic circuit, connected to the frequency-division circuit, the phase comparator and the variable delay circuit, for obtaining a logic signal based on an output of the frequency-division circuit and the control signal, and supplying the logic signal to the variable delay circuit.

Claim 12

The sync signal generating circuit according to claim 9 , wherein said control signal output controller circuit comprises: an internal clock signal generating circuit for outputting an internal clock signal; and a logic circuit, connected to the internal clock signal generating circuit, the phase comparator and the variable delay circuit, for obtaining a logic signal based on the internal clock signal and the control signal, and supplying the logic signal to the variable delay circuit.

Claim 13

The sync signal generating circuit according to claim 9 , wherein said internal circuit is a DQ buffer circuit, built in a DRAM, for outputting internal data in synchronism with the internal clock signal, and said control signal output controller circuit comprises: a self-refresh clock signal generating circuit for outputting a refresh clock signal to be used for controlling a self-refresh operation of the DRAM; and a logic circuit, connected to the self-refresh clock signal generating circuit, the phase comparator and the variable delay circuit, for obtaining a logic signal based on the refresh clock signal and the control signal, and supplying the logic signal to the variable delay circuit.

Claim 14

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a variable delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit and delivering a delayed output; a first voltage generating circuit, connected to the variable delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the variable delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages and outputting an internal clock signal; an internal circuit connected to the voltage comparing circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a first frequency-division circuit, connected to the voltage comparing circuit, for frequency-dividing the internal clock signal and delivering a frequency-division output; a second delay circuit, connected to the first frequency-division circuit, for delaying the output of the first frequency-division circuit by a second time period that is substantially equal to said first time period, and delivering a delayed output; a second frequency-division circuit, connected to the input buffer circuit, for frequency-dividing the output of the input buffer circuit and delivering a frequency-division output; and a phase comparator, connected to the second delay circuit, the second frequency-division circuit and the variable delay circuit, for comparing phases of outputs of the second delay circuit and the second frequency-division circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs to the variable delay circuit, wherein a delay time in said variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

Claim 15

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a variable delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit and delivering a delayed output; a first voltage generating circuit, connected to the variable delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the variable delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages and outputting an internal clock signal; an internal circuit connected to the voltage comparing circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a first frequency-division circuit, connected to the voltage comparing circuit, for frequency-dividing the internal clock signal and delivering a frequency-division output; a second delay circuit, connected to the first frequency-division circuit, for delaying the output of the first frequency-division circuit by a second time period that is substantially equal to said first time period, and delivering a delayed output; a second frequency-division circuit, connected to the input buffer circuit, for frequency-dividing the output of the input buffer circuit and delivering a frequency-division output; and a phase comparator, connected to the second delay circuit, the second frequency-division circuit and the variable delay circuit, for comparing phases of outputs of the second delay circuit and the second frequency-division circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs to the variable delay circuit, wherein a delay time in said variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

Claim 16

The sync signal generating circuit according to claim 13 , wherein said first time period in the first delay circuit is substantially equal to a sum of a signal delay time of the input buffer circuit relative to the external clock signal and a signal delay time of the internal circuit relative to the internal clock signal.

Claim 17

The sync signal generating circuit according to claim 13 , wherein said variable delay circuit comprises: a charge pump circuit for receiving the control signal and outputting a DC voltage corresponding to the control signal; and a third delay circuit having a power supply node and supplied with the DC voltage output from the charge pump circuit.

Claim 18

The sync signal generating circuit according to claim 15 , wherein said third delay circuit has tandem-connected inverters.

Claim 19

The sync signal generating circuit according to claim 13 , wherein said variable delay circuit comprises: a charge pump circuit for receiving the control signal and outputting a DC voltage corresponding to the control signal; tandem-connected delay circuits; and a current-limiting element inserted between each of the delay circuits and a power supply node and controlled to have a turn-on resistance varying on the basis of the DC voltage output from the charge pump circuit.

Claim 20

The sync signal generating circuit according to claim 17 , wherein each of said delay circuits is a CMOS inverter circuit.

Claim 21

The sync signal generating circuit according to claim 13 , wherein said variable delay circuit comprises: a third delay circuit connected to the first delay circuit; a counter circuit, connected to the phase comparator, for counting the control signal; and a delay control circuit, connected to the counter circuit and the third delay circuit, for controlling the third delay circuit in accordance with the output of the counter circuit.

Claim 22

The sync signal generating circuit according to claim 19 , wherein said third delay circuit comprises tandem-connected inverters, and said delay control circuit comprises a selector circuit for selecting different outputs of the inverters of the third delay circuit and delivering the selected outputs.

Claim 23

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit by a second time period and delivering a delayed output; a first voltage generating circuit, connected to the second delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the second delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing/variable delay circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages, outputting an internal clock signal, delaying the internal clock signal, and delivering a delayed output; an internal circuit connected to the voltage comparing/variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a third delay circuit, connected to the voltage comparing/variable delay circuit, for delaying the internal clock signal by a time period that is substantially equal to said first time period, and delivering a delayed output; and a phase comparator, connected to the third delay circuit and the input buffer circuit, for comparing phases of outputs of the third delay circuit and the input buffer circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs, wherein a delay time in said voltage comparing/variable delay circuit is adjusted on the basis of the control signal corresponding to the phase difference, which is output from the phase comparator.

Claim 24

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit by a second time period and delivering a delayed output; a first voltage generating circuit, connected to the second delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the second delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing/variable delay circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages, outputting an internal clock signal, delaying the internal clock signal, and delivering a delayed output; an internal circuit connected to the voltage comparing/variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a third delay circuit, connected to the voltage comparing/variable delay circuit, for delaying the internal clock signal by a time period that is substantially equal to said first time period, and delivering a delayed output; and a phase comparator, connected to the third delay circuit and the input buffer circuit, for comparing phases of outputs of the third delay circuit and the input buffer circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs, wherein a delay time in said voltage comparing/variable delay circuit is adjusted on the basis of the control signal corresponding to the phase difference, which is output from the phase comparator.

Claim 25

The sync signal generating circuit according to claim 21 , wherein said first time period in the first delay circuit is substantially equal to a sum of a signal delay time of the input buffer circuit relative to the external clock signal and a signal delay time of the internal circuit relative to the internal clock signal.

Claim 26

The sync signal generating circuit according to claim 21 , wherein said voltage comparing/variable delay circuit comprises: a charge pump circuit for receiving the control signal and outputting a DC voltage corresponding to the control signal; and a voltage comparing circuit having a power supply node and supplied with the DC voltage output from the charge pump circuit.

Claim 27

The sync signal generating circuit according to claim 21 , further comprising a control signal output controller circuit, connected to the phase comparator and the voltage comparing/variable delay circuit, for supplying the control signal from the phase comparator to the voltage comparing/variable delay circuit at a predetermined timing.

Claim 28

The sync signal generating circuit according to claim 24 , wherein said control signal output controller circuit comprises: a frequency-division circuit, connected to the first delay circuit, for frequency-dividing the external clock signal; and a logic circuit, connected to the frequency-division circuit, the phase comparator and the voltage comparing/variable delay circuit, for obtaining a logic signal based on an output of the frequency-division circuit and the control signal, and supplying the logic signal to the voltage comparing/variable delay circuit.

Claim 29

The sync signal generating circuit according to claim 24 , wherein said control signal output controller circuit comprises: an internal clock signal generating circuit; and a logic circuit, connected to the internal clock signal generating circuit and the phase comparator, for obtaining a logic signal based on the internal clock signal and the control signal, and supplying the logic signal to the voltage comparing/variable delay circuit.

Claim 30

The sync signal generating circuit according to claim 24 , wherein said internal circuit is a DQ buffer circuit, built in a DRAM, for outputting internal data in synchronism with the internal clock signal, and said control signal output controller circuit comprises: a self-refresh clock signal generating circuit for outputting a refresh clock signal to be used for controlling a self-refresh operation of the DRAM; and a logic circuit, connected to the self-refresh clock signal generating circuit and the phase comparator, for obtaining a logic signal based on the refresh clock signal and the control signal output from the phase comparator, and supplying the logic signal to the voltage comparing/variable delay circuit.

Claim 31

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit by a second time period and delivering a delayed output; a first voltage generating circuit, connected to the second delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the second delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing/variable delay circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages, outputting an internal clock signal, delaying the internal clock signal, and delivering a delayed output; an internal circuit connected to the voltage comparing/variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a first frequency-division circuit, connected to the voltage comparing/variable delay circuit, for frequency-dividing the internal clock signal and delivering a frequency-division output; a third delay circuit, connected to the first frequency-division circuit, for delaying the output of the first frequency-division circuit by a third time period that is substantially equal to said first time period, and delivering a delayed output; a second frequency-division circuit, connected to the input buffer circuit, for frequency-dividing the output of the input buffer circuit and delivering a frequency-division output; and a phase comparator, connected to the third delay circuit, the second frequency-division circuit and the voltage comparing/variable delay circuit, for comparing phases of outputs of the third delay circuit and the second frequency-division circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs to the voltage comparing/variable delay circuit, wherein a delay time in said voltage comparing/variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

Claim 32

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit by a second time period and delivering a delayed output; a first voltage generating circuit, connected to the second delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the second delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit; a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit; a voltage comparing/variable delay circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages, outputting an internal clock signal, delaying the internal clock signal, and delivering a delayed output; an internal circuit connected to the voltage comparing/variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a first frequency-division circuit, connected to the voltage comparing/variable delay circuit, for frequency-dividing the internal clock signal and delivering a frequency-division output; a third delay circuit, connected to the first frequency-division circuit, for delaying the output of the first frequency-division circuit by a third time period that is substantially equal to said first time period, and delivering a delayed output; a second frequency-division circuit, connected to the input buffer circuit, for frequency-dividing the output of the input buffer circuit and delivering a frequency-division output; and a phase comparator, connected to the third delay circuit, the second frequency-division circuit and the voltage comparing/variable delay circuit, for comparing phases of outputs of the third delay circuit and the second frequency-division circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs to the voltage comparing/variable delay circuit, wherein a delay time in said voltage comparing/variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

Claim 33

The sync signal generating circuit according to claim 28 , wherein each of said first time period in the first delay circuit and said third time period in the third delay circuit is substantially equal to a sum of a signal delay time of the input buffer circuit relative to the external clock signal and a signal delay time of the internal circuit relative to the internal clock signal.

Claim 34

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit and the input buffer circuit, for starting delaying of the output of the first delay circuit at a time of transition of a level of the output of the first delay circuit and stopping the delaying of the output of the first delay circuit at a time of transition of a level of the output of the input buffer circuit; a third delay circuit, connected to the input buffer circuit, for starting delaying of the output of the input buffer circuit at a time of transition of a level of the output of the input buffer circuit, delaying the output of the input buffer circuit by a delay time substantially equal to a delay time in the second delay circuit, and outputting a delayed output; a variable delay circuit, connected to the third delay circuit, for delaying the output of the third delay circuit and outputting an internal clock signal; an internal circuit connected to the variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a fourth delay circuit, connected to the variable delay circuit, for delaying the internal clock signal by a time period that is substantially equal to said first time period, and delivering a delayed output; and a phase comparator, connected to the fourth delay circuit and the input buffer circuit, for comparing phases of outputs of the fourth delay circuit and the input buffer circuit, and outputting to the variable delay circuit a control signal corresponding to a phase difference obtained by the comparison of the outputs, wherein a delay time in said variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

Claim 35

A sync signal generating circuit comprising: an input buffer circuit to which an external clock signal is input; a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output; a second delay circuit, connected to the first delay circuit and the input buffer circuit, for starting delaying of the output of the first delay circuit at a time of transition of a level of the output of the first delay circuit and stopping the delaying of the output of the first delay circuit at a time of transition of a level of the output of the input buffer circuit; a third delay circuit, connected to the input buffer circuit, for starting delaying of the output of the input buffer circuit at a time of transition of a level of the output of the input buffer circuit, delaying the output of the input buffer circuit by a delay time substantially equal to a delay time in the second delay circuit, and outputting a delayed output; a variable delay circuit, connected to the third delay circuit, for delaying the output of the third delay circuit and outputting an internal clock signal; an internal circuit connected to the variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal; a fourth delay circuit, connected to the variable delay circuit, for delaying the internal clock signal by a time period that is substantially equal to said first time period, and delivering a delayed output; and a phase comparator, connected to the fourth delay circuit and the input buffer circuit, for comparing phases of outputs of the fourth delay circuit and the input buffer circuit, and outputting to the variable delay circuit a control signal corresponding to a phase difference obtained by the comparison of the outputs, wherein a delay time in said variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.