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US6366148B1
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Delay locked loop circuit and method for generating internal clock signal
Assignee: Samsung Electronics Co Ltd
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Filing: 2000-11-16
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Granted: 2002-04-02
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Expires: 2020-11-16
Abstract
Abstract A delay locked loop circuit prevents occurrence of jitter and has a small chip area when it is realized as a semiconductor integrated circuit. The delay locked loop circuit includes a phase shifter, a compensation delay unit, a component coefficient extractor, a phase inverter, first and second component signal generators, and a phase mixer. In this structure, the delay locked loop circuit generates an output clock signal, the phase of which leads that of an externally-applied input clock signal by a predetermined delay time to compensate for a delay time which inevitably occurs in semiconductor integrated circuits. The phase shifter generates a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal. The compensation delay unit outputs a third clock signal, the phase of which lags that of the input clock signal by a predetermined delay time. The component coefficient extractor extracts first and second component coefficients of the third clock signal. The phase inverter inverts the phase of the second component coefficient. The first component signal generator generates a first component signal by multiplying the first component coefficient by the first clock signal. The second component signal generator generates a second component signal by multiplying the inverted second component coefficient by the second clock signal. The phase mixer mixes the first and second component signals to generate the output clock signal.
Inventors
- 👤 Kyu-hyoun Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:51
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; G; G11; G11C; G11C8/00
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
209 words
A delay locked loop circuit for receiving an input clock signal and generating an output clock signal, the output clock signal leading in phase the input clock signal by a predetermined time, the delay locked loop circuit comprising: a phase shifter for generating a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal; a compensation delay unit for outputting a third clock signal which lags the input clock signal by the predetermined time; a component coefficient extractor for extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; a phase inverter for inverting the second component coefficient to produce an inverted second component coefficient; a first component signal generator for generating a first component signal by multiplying the first component coefficient by the first clock signal; a second component signal generator for generating a second component signal by multiplying the inverted second component coefficient by the second clock signal; and a phase mixer for mixing the first and second component signals to generate the output clock signal.
Claim 2
Dependent Claim
209 words
A delay locked loop circuit for receiving an input clock signal and generating an output clock signal, the output clock signal leading in phase the input clock signal by a predetermined time, the delay locked loop circuit comprising: a phase shifter for generating a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal; a compensation delay unit for outputting a third clock signal which lags the input clock signal by the predetermined time; a component coefficient extractor for extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; a phase inverter for inverting the second component coefficient to produce an inverted second component coefficient; a first component signal generator for generating a first component signal by multiplying the first component coefficient by the first clock signal; a second component signal generator for generating a second component signal by multiplying the inverted second component coefficient by the second clock signal; and a phase mixer for mixing the first and second component signals to generate the output clock signal.
Claim 3
Dependent Claim
86 words
The delay locked loop circuit of claim 1 , wherein the component coefficient extractor comprises: a first multiplier for multiplying the first clock signal by the third clock signal; a second multiplier for multiplying the second clock signal by the third clock signal; a first low pass filter for low-pass filtering an output signal of the first multiplier to output the first component coefficient; and a second low pass filter for low-pass filtering an output signal of the second multiplier to output the second component coefficient.
Claim 4
Dependent Claim
78 words
The delay locked loop circuit of claim 1 , wherein the component coefficient extractor comprises: a phase detector for detecting a phase difference between the third clock signal and the output clock signal; a first charge pump for outputting the first component coefficient; and a second charge pump for outputting the second component coefficient, wherein the first component coefficient increases when the second component coefficient decreases and the first component coefficient decreases when the second component coefficient increases.
Claim 5
Dependent Claim
120 words
The delay locked loop circuit of claim 3 , wherein the component coefficient extractor comprises: a first voltage sensor for sensing a voltage level of the first component coefficient; a second voltage sensor for sensing a voltage level of the second component coefficient; a first exclusive OR gate for performing exclusive OR with respect to an output signal of the phase detector and an output signal of the second voltage sensor to output a signal for controlling the first charge pump; and a second exclusive OR gate for performing exclusive OR with respect to an output signal of the phase detector and an output signal of the first voltage sensor to output a signal for controlling the second charge pump.
Claim 6
Dependent Claim
209 words
A delay locked loop circuit for receiving an input clock signal and generating an output clock signal, the output clock signal leading in phase the input clock signal by a predetermined time, the delay locked loop circuit comprising: a phase shifter for generating a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal; a compensation delay unit for outputting a third clock signal which lags the input clock signal by the predetermined time; a component coefficient extractor for extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; a phase inverter for inverting the second clock signal to produce an inverted second clock signal; a first component signal generator for generating a first component signal by multiplying the first component coefficient by the first clock signal; a second component signal generator for generating a second component signal by multiplying the second component coefficient by the inverted second clock signal; and a phase mixer for mixing the first and second component signals to generate the output clock signal.
Claim 7
Dependent Claim
209 words
A delay locked loop circuit for receiving an input clock signal and generating an output clock signal, the output clock signal leading in phase the input clock signal by a predetermined time, the delay locked loop circuit comprising: a phase shifter for generating a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal; a compensation delay unit for outputting a third clock signal which lags the input clock signal by the predetermined time; a component coefficient extractor for extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; a phase inverter for inverting the second clock signal to produce an inverted second clock signal; a first component signal generator for generating a first component signal by multiplying the first component coefficient by the first clock signal; a second component signal generator for generating a second component signal by multiplying the second component coefficient by the inverted second clock signal; and a phase mixer for mixing the first and second component signals to generate the output clock signal.
Claim 8
Dependent Claim
86 words
The delay locked loop circuit of claim 5 , wherein the component coefficient extractor comprises: a first multiplier for multiplying the first clock signal by the third clock signal; a second multiplier for multiplying the second clock signal by the third clock signal; a first low pass filter for low-pass filtering an output signal of the first multiplier to output the first component coefficient; and a second low pass filter for low-pass filtering an output signal of the second multiplier to output the second component coefficient.
Claim 9
Dependent Claim
78 words
The delay locked loop circuit of claim 5 , wherein the component coefficient extractor comprises: a phase detector for detecting a phase difference between the third clock signal and the output clock signal; a first charge pump for outputting the first component coefficient; and a second charge pump for outputting the second component coefficient, wherein the first component coefficient increases when the second component coefficient decreases and the first component coefficient decreases when the second component coefficient increases.
Claim 10
Dependent Claim
120 words
The delay locked loop circuit of claim 7 , wherein the component coefficient extractor comprises: a first voltage sensor for sensing a voltage level of the first component coefficient; a second voltage sensor for sensing a voltage level of the second component coefficient; a first exclusive OR gate for performing exclusive OR with respect to an output signal of the phase detector and an output signal of the second voltage sensor to output a signal for controlling the first charge pump; and a second exclusive OR gate for performing exclusive OR with respect to an output signal of the phase detector and an output signal of the first voltage sensor to output a signal for controlling the second charge pump.
Claim 11
Dependent Claim
151 words
A delay locked loop circuit for receiving an input clock signal and for generating an output clock signal whose phase leads the input clock signal by a predetermined time period, the delay locked loop circuit comprising: a phase shifter for shifting the input clock signal to generate an in-phase component signal of the input clock signal and a quadrature component signal of the input clock signal; a delay unit for delaying the input clock signal by the predetermined time period to generate a delayed clock signal; a decomposer for decomposing the delayed clock signal into an in-phase component and a quadrature component using the in-phase component signal and the quadrature component signal, and for generating an in-phase component coefficient and a quadrature component coefficient; and a composer for composing the output clock signal with the in-phase component signal, the quadrature component signal, the in-phase component coefficient, and the quadrature component coefficient.
Claim 12
Dependent Claim
151 words
A delay locked loop circuit for receiving an input clock signal and for generating an output clock signal whose phase leads the input clock signal by a predetermined time period, the delay locked loop circuit comprising: a phase shifter for shifting the input clock signal to generate an in-phase component signal of the input clock signal and a quadrature component signal of the input clock signal; a delay unit for delaying the input clock signal by the predetermined time period to generate a delayed clock signal; a decomposer for decomposing the delayed clock signal into an in-phase component and a quadrature component using the in-phase component signal and the quadrature component signal, and for generating an in-phase component coefficient and a quadrature component coefficient; and a composer for composing the output clock signal with the in-phase component signal, the quadrature component signal, the in-phase component coefficient, and the quadrature component coefficient.
Claim 13
Dependent Claim
76 words
The delay locked loop circuit of claim 9 , wherein the decomposer includes: a first multiplier for multiplying the in-phase component signal and the delayed clock signal; a second multiplier for multiplying the quadrature component signal and the delayed clock signal; a first filter for filtering an output of the first multiplier to generate the in-phase component coefficient; and a second filter for filtering an output of the second multiplier to generate the quadrature component coefficient.
Claim 14
Dependent Claim
79 words
The delay locked loop circuit of claim 9 , wherein the composer includes: a third multiplier for multiplying the in-phase component signal and the in-phase component coefficient; a fourth multiplier for multiplying the quadrature component signal and the quadrature component coefficient, wherein one of the quadrature component signal and the quadrature component coefficient is previously inverted; a mixer for mixing an output of the third multiplier and an output of the fourth multiplier to generate the output clock signal.
Claim 15
Dependent Claim
114 words
The delay locked loop circuit of claim 9 , wherein the decomposer includes: a phase detector for detecting a phase difference between the delayed clock signal and the output clock signal; a first control unit receiving the phase difference, for varying the in-phase component coefficient such that the in-phase component coefficient increases when the quadrature component coefficient is positive and the in-phase component coefficient decreases when the quadrature component coefficient is negative; and a second control unit receiving the phase difference, for varying the quadrature component coefficient such that the quadrature component coefficient increases when the in-phase component coefficient is negative and the quadrature component coefficient decreases when the in-phase component coefficient is positive.
Claim 16
Dependent Claim
72 words
The delay locked loop circuit of claim 12 , wherein the first control unit includes: a first voltage sensor for sensing a voltage level of the in-phase component coefficient; a first inverter for inverting the phase difference provided from the phase detector in response to an output of the first voltage sensor; and a first charge pump for varying the in-phase component coefficient in response to an output of the first inverter.
Claim 17
Dependent Claim
72 words
The delay locked loop circuit of claim 12 , wherein the second control unit includes: a second voltage sensor for sensing a voltage level of the quadrature component coefficient; a second inverter for inverting the phase difference provided from the phase detector in response to an output of the second voltage sensor; and a second charge pump for varying the quadrature component coefficient in response to an output of the second inverter.
Claim 18
Independent Claim
149 words
A method of generating an output clock signal which leads in phase an input clock signal by a predetermined time, the method comprising the steps of: generating a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal; generating a third clock signal which lags the input clock signal by the predetermined time; extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; multiplying the first component coefficient by the first clock signal; multiplying the second component coefficient by the second clock signal; and mixing signals obtained from the steps of multiplying the first component coefficient and multiplying the second component coefficient to generate the output clock signal.
Claim 19
Independent Claim
149 words
A method of generating an output clock signal which leads in phase an input clock signal by a predetermined time, the method comprising the steps of: generating a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal; generating a third clock signal which lags the input clock signal by the predetermined time; extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; multiplying the first component coefficient by the first clock signal; multiplying the second component coefficient by the second clock signal; and mixing signals obtained from the steps of multiplying the first component coefficient and multiplying the second component coefficient to generate the output clock signal.
Claim 20
Dependent Claim
86 words
The method of claim 15 , wherein the step of extracting comprises the steps of: multiplying the first clock signal by the third clock signal; multiplying the second clock signal by the third clock signal; low-pass filtering a signal obtained from the step of multiplying the first clock signal by the third clock signal to generate the first component coefficient; and low-pass filtering a signal obtained from the step of multiplying the second clock signal by the third clock signal to generate the second component coefficient.
Claim 21
Dependent Claim
108 words
The method of claim 15 , wherein the step of extracting comprises the steps of: detecting a phase difference between the third clock signal and the output clock signal to generate a control signal corresponding to the phase difference; outputting the first component coefficient by charge-pumping a first signal which is controlled by the control signal and the second component coefficient; and outputting the second component coefficient by charge-pumping a second signal which is controlled by the control signal and the first component coefficient, wherein the first component coefficient increases when the second component coefficient decreases and the first component coefficient decreases when the second component coefficient increases.
Claim 22
Dependent Claim
84 words
The method of claim 17 , wherein the step of extracting comprises the steps of: sensing a voltage level of the first component coefficient to generate a first sensing signal; sensing a voltage level of the second component coefficient to generate a second sensing signal; performing exclusive OR with respect to the control signal and the second sensing signal to generate the first signal; and performing exclusive OR with respect to the control signal and the first sensing signal to generate the second signal.
Claim 23
Dependent Claim
46 words
The method of claim 15 , wherein the step of generating the second clock signal includes the steps of: shifting phase of the input clock signal to generate a phase-shifted clock signal; and inverting phase of the phase-shifted clock signal to generate the second clock signal.
Claim 24
Dependent Claim
39 words
The method of claim 15 , wherein the step of extracting includes the steps of: detecting a quadrature component coefficient of the third clock signal; and inverting phase of the quadrature component coefficient to generate the second component coefficient.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-04-01 | 2005-10-01 | 2006-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-01 | 2009-10-01 | 2010-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-01 | 2013-10-01 | 2014-04-02 | $7700.00 | Window Closed / Lapsed |