Patent US6360333B1 successfully refreshed from Google Patents.
US6360333B1
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Method and apparatus for determining a processor failure in a multiprocessor computer
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 1998-11-19
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Granted: 2002-03-19
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Expires: 2018-11-19
Abstract
Abstract A multiprocessor computer includes a fault detection scheme which detects and identifies the failure of one of the processors. Each processor is assigned a write location, which may be a unique register. During normal computer operation, each processor intermittently performs a test and stores the results of the test in the assigned write location. The stored results are compared to expected results, and an error signal is generated if the stored results differ from the expected results to indicate that one of the processors has failed.
Inventors
- 👤 Kenneth A. Jansen
- 👤 Sompong P. Olarig
- 👤 John E. Jenne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F11/07; G06F11/16; G06F11/20; G06F11/202; G06F11/2035; G06F11/2046
Claims Analysis
Total Claims: 75
Claim 1
Independent Claim
97 words
A method of determining a processor failure in a multiprocessor computer, the method comprising the acts of: (a) identifying each processor in the computer; (b) assigning a unique write location to each identified processor; (c) directing each processor to perform a given test and to store a result of the test in the respective unique write location; (d) comparing the result stored in each unique write location to a respective expected result; and (e) indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 2
Independent Claim
97 words
A method of determining a processor failure in a multiprocessor computer, the method comprising the acts of: (a) identifying each processor in the computer; (b) assigning a unique write location to each identified processor; (c) directing each processor to perform a given test and to store a result of the test in the respective unique write location; (d) comparing the result stored in each unique write location to a respective expected result; and (e) indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 3
Dependent Claim
24 words
The method, as set forth in claim 1 , wherein act (b) comprises the act of: assigning a separate register to each identified processor.
Claim 4
Dependent Claim
26 words
The method, as set forth in claim 1 , wherein act (b) comprises the act of: assigning write locations in main memory to each identified processor.
Claim 5
Dependent Claim
25 words
The method, as set forth in claim 1 , wherein act (c) comprises the act of: directing each processor to perform a floating point operation.
Claim 6
Dependent Claim
25 words
The method, as set forth in claim 1 , wherein act (c) comprises the act of: directing each processor to perform a fixed point operation.
Claim 7
Dependent Claim
24 words
The method, as set forth in claim 1 , wherein act (c) comprises the act of: directing each processor to perform a checksum operation.
Claim 8
Dependent Claim
42 words
The method, as set forth in claim 1 , comprising the act of: (f) clearing each write location in response to the stored result being the same as the expected result; and (g) repeating acts (c) through (g) at a given rate.
Claim 9
Dependent Claim
32 words
The method, as set forth in claim 7 , wherein act (c) comprises the act of: directing each processor to perform the same test each time acts (c) through (g) are repeated.
Claim 10
Dependent Claim
37 words
The method, as set forth in claim 7 , wherein act (c) comprises the act of: directing each processor to perform a test selected from a plurality of tests each time acts (c) through (g) are repeated.
Claim 11
Dependent Claim
34 words
The method, as set forth in claim 1 , wherein act (d) comprises the act of: comparing the result stored in each unique write location to a respective expected result using a hardware comparator.
Claim 12
Dependent Claim
34 words
The method, as set forth in claim 1 , wherein act (d) comprises the act of: comparing the result stored in each unique write location to a respective expected result using a software comparator.
Claim 13
Dependent Claim
19 words
The method, as set forth in claim 1 , wherein act (e) comprises the act of: generating an interrupt.
Claim 14
Dependent Claim
32 words
The method, as set forth in claim 12 , wherein act (e) comprises the act of: identifying the failure of the particular one of the identified processor in response to the interrupt.
Claim 15
Dependent Claim
27 words
The method, as set forth in claim 1 , wherein act (e) comprises the act of: alerting a user of the computer that a processor has failed.
Claim 16
Dependent Claim
27 words
The method, as set forth in claim 1 , wherein act (e) comprises the act of: disabling the failed processor while the other processors continue to operate.
Claim 17
Dependent Claim
18 words
The method, as set forth in claim 1 , wherein the acts are performed in the recited order.
Claim 18
Independent Claim
135 words
A method of determining a processor failure in a multiprocessor computer, the method comprising the acts of: (a) identifying each processor in the computer during a power up sequence; (b) assigning a unique write location to each identified processor; (c) setting a rate for directing each processor to perform a given test during normal operation of the computer; (d) repeatedly directing each processor to perform the given test and to store a result of the test in the respective unique write location in accordance with the set rate; (e) comparing the result stored in each unique write location to a respective expected result each time the given test is performed; and (f) indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 19
Independent Claim
135 words
A method of determining a processor failure in a multiprocessor computer, the method comprising the acts of: (a) identifying each processor in the computer during a power up sequence; (b) assigning a unique write location to each identified processor; (c) setting a rate for directing each processor to perform a given test during normal operation of the computer; (d) repeatedly directing each processor to perform the given test and to store a result of the test in the respective unique write location in accordance with the set rate; (e) comparing the result stored in each unique write location to a respective expected result each time the given test is performed; and (f) indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 20
Dependent Claim
24 words
The method, as set forth in claim 17 , wherein act (b) comprises the act of: assigning a separate register to each identified processor.
Claim 21
Dependent Claim
26 words
The method, as set forth in claim 17 , wherein act (b) comprises the act of: assigning write locations in main memory to each identified processor.
Claim 22
Dependent Claim
20 words
The method, as set forth in claim 17 , wherein act (c) comprises the act of: setting a fixed rate.
Claim 23
Dependent Claim
27 words
The method, as set forth in claim 17 , wherein act (c) comprises the act of: setting a variable rate each time the computer is powered up.
Claim 24
Dependent Claim
27 words
The method, as set forth in claim 17 , wherein act (c) comprises the act of: setting a rate that adaptively changes during operation of the computer.
Claim 25
Dependent Claim
25 words
The method, as set forth in claim 17 , wherein act (d) comprises the act of: directing each processor to perform a floating point operation.
Claim 26
Dependent Claim
25 words
The method, as set forth in claim 17 , wherein act (d) comprises the act of: directing each processor to perform a fixed point operation.
Claim 27
Dependent Claim
24 words
The method, as set forth in claim 17 , wherein act (d) comprises the act of: directing each processor to perform a checksum operation.
Claim 28
Dependent Claim
42 words
The method, as set forth in claim 17 , comprising the act of: (g) clearing each write location in response to the stored result being the same as the expected result; and (h) repeating acts (d) through (h) at a given rate.
Claim 29
Dependent Claim
32 words
The method, as set forth in claim 26 , wherein act (d) comprises the act of: directing each processor to perform the same test each time acts (c) through (g) are repeated.
Claim 30
Dependent Claim
37 words
The method, as set forth in claim 26 , wherein act (d) comprises the act of: directing each processor to perform a test selected from a plurality of tests each time acts (c) through (g) are repeated.
Claim 31
Dependent Claim
34 words
The method, as set forth in claim 17 , wherein act (e) comprises the act of: comparing the result stored in each unique write location to a respective expected result using a hardware comparator.
Claim 32
Dependent Claim
34 words
The method, as set forth in claim 17 , wherein act (e) comprises the act of: comparing the result stored in each unique write location to a respective expected result using a software comparator.
Claim 33
Dependent Claim
19 words
The method, as set forth in claim 17 , wherein act (f) comprises the act of: generating an interrupt.
Claim 34
Dependent Claim
32 words
The method, as set forth in claim 31 , wherein act (f) comprises the act of: identifying the failure of the particular one of the identified processors in response to the interrupt.
Claim 35
Dependent Claim
29 words
The method, as set forth in claim 17 , wherein act (f) comprises the act of: updating a memory location with an error signal to indicate a processor failure.
Claim 36
Dependent Claim
34 words
The method, as set forth in claim 33 , wherein act (f) further comprises the act of: identifying the failure of the particular one of the identified processors in response to the error signal.
Claim 37
Dependent Claim
27 words
The method, as set forth in claim 17 , wherein act (f) comprises the act of: alerting a user of the computer that a processor has failed.
Claim 38
Dependent Claim
27 words
The method, as set forth in claim 17 , wherein act (f) comprises the act of: disabling the failed processor while the other processors continue to operate.
Claim 39
Dependent Claim
18 words
The method, as set forth in claim 17 , wherein the acts are performed in the recited order.
Claim 40
Independent Claim
103 words
A method of determining a failure of an intelligent device in a computer, the method comprising the acts of: (a) identifying each intelligent device in the computer; (b) assigning a unique write location to each identified intelligent device; (c) directing each intelligent device to perform a given test and to store a result of the test in the respective unique write location; (d) comparing the result stored in each unique write location to a respective expected result; and (e) indicating a failure of a particular one of the identified intelligent devices in response to the stored result being different than the expected result.
Claim 41
Independent Claim
103 words
A method of determining a failure of an intelligent device in a computer, the method comprising the acts of: (a) identifying each intelligent device in the computer; (b) assigning a unique write location to each identified intelligent device; (c) directing each intelligent device to perform a given test and to store a result of the test in the respective unique write location; (d) comparing the result stored in each unique write location to a respective expected result; and (e) indicating a failure of a particular one of the identified intelligent devices in response to the stored result being different than the expected result.
Claim 42
Dependent Claim
42 words
The method, as set forth in claim 38 , comprising the act of: (f) clearing each write location in response to the stored result being the same as the expected result; and (g) repeating acts (c) through (g) at a given rate.
Claim 43
Dependent Claim
16 words
The method, as set forth in claim 38 , wherein the intelligent device comprises a microprocessor.
Claim 44
Dependent Claim
17 words
The method, as set forth in claim 38 , wherein the intelligent device comprises a memory controller.
Claim 45
Independent Claim
99 words
An apparatus for detecting a failed processor of a multiprocessor computer, the apparatus comprising: means for identifying each processor in the computer; means for assigning a unique write location to each identified processor; means for directing each processor to perform a given test and to store a result of the test in the respective unique write location; means for comparing the result stored in each unique write location to a respective expected result; and means for indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 46
Independent Claim
99 words
An apparatus for detecting a failed processor of a multiprocessor computer, the apparatus comprising: means for identifying each processor in the computer; means for assigning a unique write location to each identified processor; means for directing each processor to perform a given test and to store a result of the test in the respective unique write location; means for comparing the result stored in each unique write location to a respective expected result; and means for indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 47
Dependent Claim
31 words
The apparatus, as set forth in claim 42 , further comprising: means for setting a rate for directing each processor to perform a given test during normal operation of the computer.
Claim 48
Dependent Claim
30 words
The apparatus, as set forth in claim 42 , further comprising: means for clearing each write location in response to the stored result being the same as the expected result.
Claim 49
Dependent Claim
100 words
A tangible medium containing a software program for detecting a failed processor of a multiprocessor computer comprising: a routine for assigning a unique write location to each processor in the computer; a routine for directing each processor to perform a given test and to store a result of the test in the respective unique write location; a routine for comparing the result stored in each unique write location to a respective expected result; and a routine for indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 50
Dependent Claim
100 words
A tangible medium containing a software program for detecting a failed processor of a multiprocessor computer comprising: a routine for assigning a unique write location to each processor in the computer; a routine for directing each processor to perform a given test and to store a result of the test in the respective unique write location; a routine for comparing the result stored in each unique write location to a respective expected result; and a routine for indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 51
Dependent Claim
24 words
The tangible medium, as set forth in claim 45 , wherein the routine for indicating a failure comprises: a routine for generating an interrupt.
Claim 52
Dependent Claim
26 words
The tangible medium, as set forth in claim 45 , wherein the routine for indicating a failure comprises: a routine for recording the failure in memory.
Claim 53
Dependent Claim
126 words
A network comprising: a plurality of interconnected computers, wherein at least one of the plurality of interconnected computers comprises a multiprocessor computer, the multiprocessor computer comprising means for detecting a failed processor of a multiprocessor computer, the detecting means comprising: means for identifying each processor in the multiprocessor computer; means for assigning a unique write location to each identified processor; means for directing each processor to perform a given test and to store a result of the test in the respective unique write location; means for comparing the result stored in each unique write location to a respective expected result; and means for indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 54
Dependent Claim
126 words
A network comprising: a plurality of interconnected computers, wherein at least one of the plurality of interconnected computers comprises a multiprocessor computer, the multiprocessor computer comprising means for detecting a failed processor of a multiprocessor computer, the detecting means comprising: means for identifying each processor in the multiprocessor computer; means for assigning a unique write location to each identified processor; means for directing each processor to perform a given test and to store a result of the test in the respective unique write location; means for comparing the result stored in each unique write location to a respective expected result; and means for indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 55
Dependent Claim
35 words
The network, as set forth in claim 48 , wherein the detecting means further comprises: means for setting a rate for directing each processor to perform a given test during normal operation of the computer.
Claim 56
Dependent Claim
34 words
The network, as set forth in claim 48 , wherein the detecting means further comprises: means for clearing each write location in response to the stored result being the same as the expected result.
Claim 57
Dependent Claim
103 words
A computer comprising: a plurality of microprocessors, each microprocessor repeatedly performing a given test during operation of the computer; a plurality of registers, each register being assigned to a selected one of the plurality of microprocessors for storing a result of each given test performed by the respective microprocessor; and a comparator coupled to the plurality of registers to receive the result stored in each register, the comparator comparing each stored result with an expected result and generating an signal indicative of a failed microprocessor in response to one of the stored results being different than a respective one of the expected results.
Claim 58
Dependent Claim
103 words
A computer comprising: a plurality of microprocessors, each microprocessor repeatedly performing a given test during operation of the computer; a plurality of registers, each register being assigned to a selected one of the plurality of microprocessors for storing a result of each given test performed by the respective microprocessor; and a comparator coupled to the plurality of registers to receive the result stored in each register, the comparator comparing each stored result with an expected result and generating an signal indicative of a failed microprocessor in response to one of the stored results being different than a respective one of the expected results.
Claim 59
Independent Claim
111 words
A method of determining a processor failure in a multiprocessor computer, the method comprising the acts of: (a) identifying each processor in the computer; (b) assigning a plurality of unique write locations to each identified processor; (c) directing each processor to perform a plurality of given tests and to store a result of each of the plurality of given tests in a respective one of the respective plurality of unique write locations; (d) comparing the result stored in each write location to a respective expected result; and (e) indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 60
Independent Claim
111 words
A method of determining a processor failure in a multiprocessor computer, the method comprising the acts of: (a) identifying each processor in the computer; (b) assigning a plurality of unique write locations to each identified processor; (c) directing each processor to perform a plurality of given tests and to store a result of each of the plurality of given tests in a respective one of the respective plurality of unique write locations; (d) comparing the result stored in each write location to a respective expected result; and (e) indicating a failure of a particular one of the identified processors in response to the stored result being different than the expected result.
Claim 61
Dependent Claim
26 words
The method, as set forth in claim 52 , wherein act (b) comprises the act of: assigning a plurality of separate registers to each identified processor.
Claim 62
Dependent Claim
29 words
The method, as set forth in claim 52 , wherein act (b) comprises the act of: assigning a plurality of write locations in main memory to each identified processor.
Claim 63
Dependent Claim
25 words
The method, as set forth in claim 52 , wherein act (c) comprises the act of: directing each processor to perform a floating point operation.
Claim 64
Dependent Claim
25 words
The method, as set forth in claim 52 , wherein act (c) comprises the act of: directing each processor to perform a fixed point operation.
Claim 65
Dependent Claim
24 words
The method, as set forth in claim 52 , wherein act (c) comprises the act of: directing each processor to perform a checksum operation.
Claim 66
Dependent Claim
42 words
The method, as set forth in claim 52 , comprising the act of: (f) clearing each write location in response to the stored result being the same as the expected result; and (g) repeating acts (c) through (g) at a given rate.
Claim 67
Dependent Claim
34 words
The method, as set forth in claim 58 , wherein act (c) comprises the act of: directing each processor to perform the same plurality of tests each time acts (c) through (g) are repeated.
Claim 68
Dependent Claim
40 words
The method, as set forth in claim 58 , wherein act (c) comprises the act of: directing each processor to perform a plurality of tests selected from a greater plurality of tests each time acts (c) through (g) are repeated.
Claim 69
Dependent Claim
34 words
The method, as set forth in claim 52 , wherein act (d) comprises the act of: comparing the result stored in each unique write location to a respective expected result using a hardware comparator.
Claim 70
Dependent Claim
34 words
The method, as set forth in claim 52 , wherein act (d) comprises the act of: comparing the result stored in each unique write location to a respective expected result using a software comparator.
Claim 71
Dependent Claim
19 words
The method, as set forth in claim 52 , wherein act (e) comprises the act of: generating an interrupt.
Claim 72
Dependent Claim
32 words
The method, as set forth in claim 63 , wherein act (e) comprises the act of: identifying the failure of the particular one of the identified processor in response to the interrupt.
Claim 73
Dependent Claim
27 words
The method, as set forth in claim 52 , wherein act (e) comprises the act of: alerting a user of the computer that a processor has failed.
Claim 74
Dependent Claim
27 words
The method, as set forth in claim 52 , wherein act (e) comprises the act of: disabling the failed processor while the other processors continue to operate.
Claim 75
Dependent Claim
18 words
The method, as set forth in claim 52 , wherein the acts are performed in the recited order.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-03-18 | 2005-09-17 | 2006-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-18 | 2009-09-17 | 2010-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-18 | 2013-09-17 | 2014-03-19 | $7700.00 | Window Closed / Lapsed |