US6358798B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming gate electrode by damascene process
Assignee: United Microelectronics Corp
•
Filing: 2000-09-06
•
Granted: 2002-03-19
•
Expires: 2020-09-06
Abstract
Abstract The present invention is a method for forming a gate electrode of a transistor in integrated circuits, where the gate electrode is formed by a damascene process. First, a substrate is provided with a gate dielectric layer thereon and a first gate layer is formed on the gate dielectric layer. Next, a first silicon oxide layer is deposited on the first gate layer and an opening through the first silicon oxide layer is formed by an etching process. Then, a first spacer is formed on sidewalls of the first silicon oxide layer in the opening and then the opening is filled with a second gate layer. Following, the first silicon oxide layer and the first spacer are removed to form a gate structure. Next, the first gate layer and the gate dielectric layer around the gate structure are removed. Then, a lightly doped drain, a second spacer, and a source/drain region are formed sequentially in the transistor.
Inventors
- 👤 Chin-Yang Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
137 words
A method for forming a metal oxide semiconductor (MOS) transistor, said method comprising: providing a substrate with a gate dielectric layer thereon; forming a first gate layer on said gate dielectric layer; depositing a first silicon oxide layer on said first gate layer; etching said first silicon oxide layer to expose a portion of said first gate layer to form an opening; forming a first spacer on sidewalls of said first silicon oxide layer in said opening; filling said opening with a second gate layer; removing said first silicon oxide layer and said first spacer to form a gate structure; removing said first gate layer and said gate dielectric layer uncovered by said second gate layer; and sequentially forming a lightly doped drain (LDD), a second spacer, and a source/drain region in said metal oxide semiconductor transistor.
Claim 2
Independent Claim
137 words
A method for forming a metal oxide semiconductor (MOS) transistor, said method comprising: providing a substrate with a gate dielectric layer thereon; forming a first gate layer on said gate dielectric layer; depositing a first silicon oxide layer on said first gate layer; etching said first silicon oxide layer to expose a portion of said first gate layer to form an opening; forming a first spacer on sidewalls of said first silicon oxide layer in said opening; filling said opening with a second gate layer; removing said first silicon oxide layer and said first spacer to form a gate structure; removing said first gate layer and said gate dielectric layer uncovered by said second gate layer; and sequentially forming a lightly doped drain (LDD), a second spacer, and a source/drain region in said metal oxide semiconductor transistor.
Claim 3
Dependent Claim
22 words
The method according to claim 1 , wherein said gate dielectric layer is made of silicon oxide by using thermal oxidation method.
Claim 4
Dependent Claim
22 words
The method according to claim 1 , wherein said first gate layer is made of polysilicon by a chemical vapor deposition process.
Claim 5
Dependent Claim
22 words
The method according to claim 1 , wherein said first gate layer has a thickness of between about 200 to 500 angstroms.
Claim 6
Dependent Claim
21 words
The method according to claim 1 , wherein said opening is on an active region of said metal oxide semiconductor transistor.
Claim 7
Dependent Claim
40 words
The method according to claim 1 , wherein steps of forming said first spacer comprises: depositing a conformal second silicon oxide layer over said substrate; and blanket etching back said second silicon oxide layer to expose said first gate layer.
Claim 8
Dependent Claim
22 words
The method according to claim 1 , wherein said second gate layer is made of polysilicon by a chemical vapor deposition process.
Claim 9
Independent Claim
189 words
A method for forming a gate transistor, said method comprising: providing a substrate with a gate dielectric layer thereon, wherein said gate dielectric layer is made of silicon oxide by using thermal oxidation method; depositing a first gate layer on said gate dielectric layer, wherein said first gate layer is made of polysilicon by a chemical vapor deposition process; forming a first silicon oxide layer on said first gate layer; etching said first silicon oxide layer to expose a portion of said first gate layer to form an opening, wherein said opening is on an active region of said gate transistor; forming a first spacer on sidewalls of said first silicon oxide layer in said opening; filling said opening with a second gate layer, wherein said second gate layer is made of polysilicon by a chemical vapor deposition process; removing said first silicon oxide layer and said first spacer to form a gate structure; removing said first gate layer and said gate dielectric layer uncovered by said second gate layer; and sequentially forming a lightly doped drain (LDD), a second spacer, and a source/drain region in said gate transistor.
Claim 10
Independent Claim
189 words
A method for forming a gate transistor, said method comprising: providing a substrate with a gate dielectric layer thereon, wherein said gate dielectric layer is made of silicon oxide by using thermal oxidation method; depositing a first gate layer on said gate dielectric layer, wherein said first gate layer is made of polysilicon by a chemical vapor deposition process; forming a first silicon oxide layer on said first gate layer; etching said first silicon oxide layer to expose a portion of said first gate layer to form an opening, wherein said opening is on an active region of said gate transistor; forming a first spacer on sidewalls of said first silicon oxide layer in said opening; filling said opening with a second gate layer, wherein said second gate layer is made of polysilicon by a chemical vapor deposition process; removing said first silicon oxide layer and said first spacer to form a gate structure; removing said first gate layer and said gate dielectric layer uncovered by said second gate layer; and sequentially forming a lightly doped drain (LDD), a second spacer, and a source/drain region in said gate transistor.
Claim 11
Dependent Claim
22 words
The method according to claim 8 , wherein said first gate layer has a thickness of between about 200 to 500 angstroms.
Claim 12
Dependent Claim
40 words
The method according to claim 8 , wherein steps of forming said first spacer comprises: depositing a conformal second silicon oxide layer over said substrate; and blanket etching back said second silicon oxide layer to expose said first gate layer.
Claim 13
Independent Claim
117 words
A method for forming a gate electrode of metal oxide semiconductor transistor, said method comprising: providing a substrate with a gate dielectric layer thereon, wherein said gate dielectric layer is made of silicon oxide by using thermal oxidation method; forming a first gate layer on said gate dielectric layer; depositing a first silicon oxide layer on said first gate layer; etching said first silicon oxide layer to expose a portion of said first gate layer to form an opening; forming a first spacer on sidewalls of said first silicon oxide layer in said opening; filling said opening with a second gate layer; removing said first silicon oxide layer and said first spacer to form a gate structure.
Claim 14
Independent Claim
117 words
A method for forming a gate electrode of metal oxide semiconductor transistor, said method comprising: providing a substrate with a gate dielectric layer thereon, wherein said gate dielectric layer is made of silicon oxide by using thermal oxidation method; forming a first gate layer on said gate dielectric layer; depositing a first silicon oxide layer on said first gate layer; etching said first silicon oxide layer to expose a portion of said first gate layer to form an opening; forming a first spacer on sidewalls of said first silicon oxide layer in said opening; filling said opening with a second gate layer; removing said first silicon oxide layer and said first spacer to form a gate structure.
Claim 15
Dependent Claim
22 words
The method according to claim 11 , wherein said first gate layer is made of polysilicon by a chemical vapor deposition process.
Claim 16
Dependent Claim
23 words
The method according to claim 11 , wherein said first gate layer is in a thickness of between about 200 to 500 angstroms.
Claim 17
Dependent Claim
40 words
The method according to claim 11 , wherein steps of forming said first spacer comprises: depositing a conformal second silicon oxide layer over said substrate; and blanket etching back said second silicon oxide layer to expose said first gate layer.
Claim 18
Dependent Claim
22 words
The method according to claim 11 , wherein said second gate layer is made of polysilicon by a chemical vapor deposition process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-18 | 2005-09-17 | 2006-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-18 | 2009-09-17 | 2010-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-18 | 2013-09-17 | 2014-03-19 | $7700.00 | Window Closed / Lapsed |