US6356312B1
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US
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MPEG decoder and decoding control method for handling system clock discontinuity
Assignee: LG Electronics Inc
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Filing: 1998-12-22
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Granted: 2002-03-12
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Expires: 2018-12-22
Abstract
Abstract An apparatus and method for MPEG decoding are disclosed which control decoding without reference to the system time clock for a predetermined time period during a discontinuity of system time clock. Thus, an error caused by inconsistency between the system time clock and the time stamp due to delay of the video buffer is eliminated, thereby allowing normal decoding with A/V lip-synchronization.
Inventors
- 👤 Hwa Young Lyu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:37
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/4302; H04N21/4305; H04N21/80; H04N21/85; H04N21/854; H04N21/8547; H04N21/20; H04N21/23; H04N21/242; H04N21/4307; H04N21/43072; H04N21/434; H04N21/4341; H04N5/00; H04N5/04; H04N21/41; H04N21/426
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
196 words
A MPEG decoder comprising: an input signal processor restoring a system time clock from the input bit streams, said input signal processor generating and outputting a discontinuity signal if a system time clock discontinuity occurs; a mode signal generator generating and outputting a first mode signal for a predetermined time period when the discontinuity signal is received; a decoder decoding the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, wherein the decoded input bit streams include data received before the system time clock discontinuity in the input bit streams, wherein the decoder comprises, an audio decoder decoding audio bit streams from the input bit streams, and a video decoder decoding video bit streams from the input bit streams; an audio buffer temporarily storing audio bit streams received from the input signal processor and outputting the audio bit streams to the decoder; and a video buffer temporarily storing video bit streams received from the input signal processor and outputting the video bit streams to the decoder, wherein the temporarily stored audio and video bit streams are not cleared responsive to the system time clock discontinuity.
Claim 2
Dependent Claim
196 words
A MPEG decoder comprising: an input signal processor restoring a system time clock from the input bit streams, said input signal processor generating and outputting a discontinuity signal if a system time clock discontinuity occurs; a mode signal generator generating and outputting a first mode signal for a predetermined time period when the discontinuity signal is received; a decoder decoding the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, wherein the decoded input bit streams include data received before the system time clock discontinuity in the input bit streams, wherein the decoder comprises, an audio decoder decoding audio bit streams from the input bit streams, and a video decoder decoding video bit streams from the input bit streams; an audio buffer temporarily storing audio bit streams received from the input signal processor and outputting the audio bit streams to the decoder; and a video buffer temporarily storing video bit streams received from the input signal processor and outputting the video bit streams to the decoder, wherein the temporarily stored audio and video bit streams are not cleared responsive to the system time clock discontinuity.
Claim 3
Dependent Claim
48 words
An apparatus of claim 1 , wherein the mode signal generator generates and outputs a second mode signal when the discontinuity signal is not received, and wherein the decoder decodes the input bit streams in reference to the system time clock if the second mode signal is received.
Claim 4
Dependent Claim
32 words
An apparatus of claim 1 , further comprising: a data buffer temporarily storing the input bit streams received from the input signal processor and outputting the input bit streams to the decoder.
Claim 5
Dependent Claim
28 words
An apparatus of claim 3 , wherein the predetermined time period is greater than a delay time of the data buffer caused by the system time clock discontinuity.
Claim 6
Dependent Claim
16 words
An apparatus of claim 3 , wherein the predetermined time period is greater than 0.5 seconds.
Claim 7
Dependent Claim
21 words
An apparatus of claim 1 , further comprising: a monitor receiving and displaying the decoded input bit streams from the decoder.
Claim 8
Dependent Claim
19 words
An apparatus of claim 1 , wherein the input bit stream is fully decoded during the predetermined time period.
Claim 9
Dependent Claim
346 words
A MPEG decoder comprising: an input signal processor restoring a system time clock from the input bit streams, said input signal processor generating and outputting a discontinuity signal if a system time clock discontinuity occurs; a mode signal generator generating and outputting a first mode signal for a predetermined time period when the discontinuity signal is received, and generating and outputting a second mode signal when the discontinuity signal is not received; a audio decoder decoding audio bit streams from the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, and decoding the audio bit streams in reference to the system time clock if the second mode signal is received; a video decoder decoding video bit streams from the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, and decoding the video bit streams in reference to the system time clock if the second mode signal is received, wherein at least one of the audio and video decoder decodes already received portions of the corresponding one of the audio and video bit streams when the first mode signal is received; a data buffer temporarily storing the input bit streams received from the input signal processor and outputting the input bit streams to the decoder, wherein the data buffer comprises, an audio buffer temporarily storing the audio bit streams received from the input signal processor and outputting the audio bit streams to the decoder, and a video buffer temporarily storing the video bit streams received from the input signal processor and outputting the video bit streams to the decoder; and a monitor receiving and displaying the decoded input bit streams from the decoder, wherein the predetermined time period is greater than a delay time of the data buffer caused by the system time clock discontinuity, wherein the audio and video bit streams are fully decoded during the predetermined time period, and wherein the audio and video buffers are not cleared responsive to the first signal.
Claim 10
Dependent Claim
346 words
A MPEG decoder comprising: an input signal processor restoring a system time clock from the input bit streams, said input signal processor generating and outputting a discontinuity signal if a system time clock discontinuity occurs; a mode signal generator generating and outputting a first mode signal for a predetermined time period when the discontinuity signal is received, and generating and outputting a second mode signal when the discontinuity signal is not received; a audio decoder decoding audio bit streams from the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, and decoding the audio bit streams in reference to the system time clock if the second mode signal is received; a video decoder decoding video bit streams from the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, and decoding the video bit streams in reference to the system time clock if the second mode signal is received, wherein at least one of the audio and video decoder decodes already received portions of the corresponding one of the audio and video bit streams when the first mode signal is received; a data buffer temporarily storing the input bit streams received from the input signal processor and outputting the input bit streams to the decoder, wherein the data buffer comprises, an audio buffer temporarily storing the audio bit streams received from the input signal processor and outputting the audio bit streams to the decoder, and a video buffer temporarily storing the video bit streams received from the input signal processor and outputting the video bit streams to the decoder; and a monitor receiving and displaying the decoded input bit streams from the decoder, wherein the predetermined time period is greater than a delay time of the data buffer caused by the system time clock discontinuity, wherein the audio and video bit streams are fully decoded during the predetermined time period, and wherein the audio and video buffers are not cleared responsive to the first signal.
Claim 11
Dependent Claim
52 words
An apparatus of claim 8 , wherein the input signal processor restores time stamps based upon the system time clock from the input bit streams; and wherein the audio and video decoder decode the audio and video bit streams, respectively based upon the time stamps if the second mode signal is received.
Claim 12
Dependent Claim
202 words
A MPEG decoding method comprising: restoring a system time clock from the input bit streams, generating and outputting a discontinuity signal if a system time clock discontinuity occurs; generating and outputting a first mode signal for a predetermined time period when the discontinuity signal is received; decoding the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, wherein the decoding the input bit streams decodes already received portions of the input bit stream during the predetermined time period upon receipt of the first mode signal; and temporarily storing the input bit streams prior to decoding and outputting the input bit streams to be decoded, wherein the input bit stream is fully decoded during the predetermined time period, and wherein the temporarily storing the input bit streams further comprises, temporarily storing audio bit streams from the input bit stream prior to decoding and outputting the input bit streams to be decoded, and temporarily storing video bit streams from the input bit stream prior to decoding and outputting the video bit streams to the decoder, wherein the temporarily stored audio and video bit streams are not cleared responsive to the first mode signal.
Claim 13
Dependent Claim
202 words
A MPEG decoding method comprising: restoring a system time clock from the input bit streams, generating and outputting a discontinuity signal if a system time clock discontinuity occurs; generating and outputting a first mode signal for a predetermined time period when the discontinuity signal is received; decoding the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, wherein the decoding the input bit streams decodes already received portions of the input bit stream during the predetermined time period upon receipt of the first mode signal; and temporarily storing the input bit streams prior to decoding and outputting the input bit streams to be decoded, wherein the input bit stream is fully decoded during the predetermined time period, and wherein the temporarily storing the input bit streams further comprises, temporarily storing audio bit streams from the input bit stream prior to decoding and outputting the input bit streams to be decoded, and temporarily storing video bit streams from the input bit stream prior to decoding and outputting the video bit streams to the decoder, wherein the temporarily stored audio and video bit streams are not cleared responsive to the first mode signal.
Claim 14
Dependent Claim
42 words
A method of claim 10 , further comprising: generating and outputting a second mode signal when the discontinuity signal is not received; and decoding the input bit streams in reference to the system time clock if the second mode signal is received.
Claim 15
Dependent Claim
104 words
A method of claim 10 , wherein the decoding further comprises: decoding audio bit streams from the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, and decoding the audio bit streams in reference to the system time clock if the second mode signal is received; and decoding video bit streams from the input bit streams based upon a basic synchronization for the predetermined time period if the first mode signal is received, and decoding the video bit streams in reference to the system time clock if the second mode signal is received.
Claim 16
Dependent Claim
28 words
A method of claim 10 , wherein the predetermined time period is greater than a delay time of the data buffer caused by the system time clock discontinuity.
Claim 17
Dependent Claim
16 words
A method of claim 10 , wherein the predetermined time period is greater than 0.5 seconds.
Claim 18
Dependent Claim
51 words
A method of claim 10 , further comprising: transmitting time stamps based upon the system time clock with flags in the same bus as the input bit streams, if the data type is audio/video bit streams; and receiving and testing the time stamps from the input bit streams using the flags.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-11 | 2005-09-10 | 2006-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-11 | 2009-09-10 | 2010-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-11 | 2013-09-10 | 2014-03-12 | $7700.00 | Window Closed / Lapsed |