Portable integrated switching power amplifier

Claim 2

A high efficiency multiple power level power amplifier comprising: at least one input amplifier stage configured to generate a first output signal from a first input signal; at least one output amplifier stage configured to receive the first output signal and generate a second output signal therefrom; a PIN diode network in electrical communication with the at least one output and at least one input amplifier stages and configured to transform an interstage impedance between the at least one input amplifier stage and the at least one output amplifier stage in response to a second input signal; and an inverter network in electrical communication with the PIN diode network and configured to generate the second input signal to selectively enable and disable the PIN diode network such that the PIN diode network is capable of controlling the interstage impedance between the at least one input and the at least one output amplifier stages to establish a desired AC load line for the high efficiency multiple power level power amplifier.

Claim 3

The high efficiency multiple power level power amplifier according to claim 1 wherein the inverter network comprises a GaAs heterojunction bipolar transistor.

Claim 4

A high efficiency multiple power level power amplifier comprising: at least one input amplifier stage configured to generate a first output signal from a first input signal; at least one output amplifier stage configured to receive the first output signal and generate a second output signal therefrom; and a PIN diode network in electrical communication with the at least one output and at least one input amplifier stages and configured to transform an interstage impedance between the at least one input amplifier stage and the at least one output amplifier stage in response to a second input signal, wherein the at least one output amplifier stage is responsive to the second input signal such that the at least one output amplifier stage can be selectively turned on and off to vary the output power level of the high efficiency multiple power level power amplifier.

Claim 5

A high efficiency multiple power level power amplifier comprising: at least one input amplifier stage configured to generate a first output signal from a first input signal; at least one output amplifier stage configured to receive the first output signal and generate a second output signal therefrom; and a PIN diode network in electrical communication with the at least one output and at least one input amplifier stages and configured to transform an interstage impedance between the at least one input amplifier stage and the at least one output amplifier stage in response to a second input signal, wherein the at least one output amplifier stage is responsive to the second input signal such that the at least one output amplifier stage can be selectively turned on and off to vary the output power level of the high efficiency multiple power level power amplifier.

Claim 6

A high efficiency multiple power level power amplifier comprising: at least one input amplifier stage configured to generate a first output signal from a first input signal; at least one output amplifier stage configured to receive the first output signal and generate a second output signal therefrom; a PIN diode network in electrical communication with the at least one output and at least one input amplifier stages and configured to transform an interstage impedance between the at least one input amplifier stage and the at least one output amplifier stage in response to a second input signal; and a plurality of impedance transformation networks in electrical communication with the PIN diode network such that the plurality of impedance transformation networks can achieve a first impedance level when the PIN diode network is enabled and further such that the plurality of impedance transformation networks can achieve a second impedance level when the PIN diode network is disabled, wherein the first and second impedance levels are capable of maintaining a desired gain and linearity characteristic at each output power level for the high efficiency multiple power level power amplifier.

Claim 7

A high efficiency multiple power level power amplifier comprising: at least one input amplifier stage configured to generate a first output signal from a first input signal; at least one output amplifier stage configured to receive the first output signal and generate a second output signal therefrom; a PIN diode network in electrical communication with the at least one output and at least one input amplifier stages and configured to transform an interstage impedance between the at least one input amplifier stage and the at least one output amplifier stage in response to a second input signal; and a plurality of impedance transformation networks in electrical communication with the PIN diode network such that the plurality of impedance transformation networks can achieve a first impedance level when the PIN diode network is enabled and further such that the plurality of impedance transformation networks can achieve a second impedance level when the PIN diode network is disabled, wherein the first and second impedance levels are capable of maintaining a desired gain and linearity characteristic at each output power level for the high efficiency multiple power level power amplifier.

Claim 8

The high efficiency multiple power level power amplifier according to claim 4 wherein the at least one input amplifier stage comprises a GaAs heterojunction bipolar transistor.

Claim 9

The high efficiency multiple power level power amplifier according to claim 5 wherein the at least one output amplifier stage comprises a GaAs heterojunction bipolar transistor.

Claim 10

A high efficiency multiple power level power amplifier comprising: at least one input amplifier stage configured to generate a first output signal from a first input signal; at least one output amplifier stage configured to receive the first output signal and generate a second output signal therefrom; and a PIN diode network in electrical communication with the at least one output and at least one input amplifier stages and configured to transform an interstage impedance between the at least one input amplifier stage and the at least one output amplifier stage in response to a second input signal, wherein the PIN diode network is configured to be integrated with a GaAs HBT integrated circuit.

Claim 11

A high efficiency multiple power level power amplifier comprising: at least one input amplifier stage configured to generate a first output signal from a first input signal; at least one output amplifier stage configured to receive the first output signal and generate a second output signal therefrom; and a PIN diode network in electrical communication with the at least one output and at least one input amplifier stages and configured to transform an interstage impedance between the at least one input amplifier stage and the at least one output amplifier stage in response to a second input signal, wherein the PIN diode network is configured to be integrated with a GaAs HBT integrated circuit.

Claim 12

A high efficiency multiple power level power amplifier comprising: a first amplifier transistor configured to generate a first amplified signal from a first input signal; an impedance matching network in electrical communication with the first amplifier transistor and configured to receive the first amplified signal and generate a processed signal therefrom; a second amplifier transistor in electrical communication with the impedance matching network and configured to receive the processed signal and generate a second amplified signal; an impedance transformation network coupled to the impedance matching network; a PIN diode network in electrical communication with the second amplifier transistor and the impedance transformation network; and an inverter network in electrical communication with the PIN diode network and configured to disable the PIN diode network such that the impedance transformation network is capable of varying the impedance characteristics of the impedance matching network to establish a first impedance level and further configured to enable the PIN diode network such that the impedance transformation network is capable of varying the impedance characteristics of the impedance matching network to establish a second impedance level.

Claim 13

A high efficiency multiple power level power amplifier comprising: a first amplifier transistor configured to generate a first amplified signal from a first input signal; an impedance matching network in electrical communication with the first amplifier transistor and configured to receive the first amplified signal and generate a processed signal therefrom; a second amplifier transistor in electrical communication with the impedance matching network and configured to receive the processed signal and generate a second amplified signal; an impedance transformation network coupled to the impedance matching network; a PIN diode network in electrical communication with the second amplifier transistor and the impedance transformation network; and an inverter network in electrical communication with the PIN diode network and configured to disable the PIN diode network such that the impedance transformation network is capable of varying the impedance characteristics of the impedance matching network to establish a first impedance level and further configured to enable the PIN diode network such that the impedance transformation network is capable of varying the impedance characteristics of the impedance matching network to establish a second impedance level.

Claim 14

The high efficiency multiple power level power amplifier according to claim 8 wherein the matching network is further configured to maintain a desired gain and linearity characteristic at a first power amplifier output power level.

Claim 15

The high efficiency multiple power level power amplifier according to claim 9 wherein the impedance matching network and the impedance transformation network are configured to yield a combined matching impedance sufficient to maintain a desired gain and linearity characteristic at a second power amplifier output power level.

Claim 16

The high efficiency multiple power level power amplifier according to claim 8 wherein the inverter network is further configured to disable the second amplifier transistor simultaneously with the enablement of the PIN diode network.

Claim 17

It A high efficiency multiple power level power amplifier comprising: means for preamplifying a first input signal to produce a first output signal; means for amplifying the first output signal to produce an amplified output signal; means for matching an output impedance of the preamplifying means to an input impedance of the amplifying means; means for transforming an impedance associated with the impedance matching means; and a PIN diode network configured to selectively enable and disable the transforming means to maintain a desired gain and linearity characteristic at a plurality of output power levels for the high efficiency multiple power level power amplifier.

Claim 18

It A high efficiency multiple power level power amplifier comprising: means for preamplifying a first input signal to produce a first output signal; means for amplifying the first output signal to produce an amplified output signal; means for matching an output impedance of the preamplifying means to an input impedance of the amplifying means; means for transforming an impedance associated with the impedance matching means; and a PIN diode network configured to selectively enable and disable the transforming means to maintain a desired gain and linearity characteristic at a plurality of output power levels for the high efficiency multiple power level power amplifier.

Claim 19

The high efficiency multiple power level power amplifier according to claim 12 wherein the preamplifying means, amplifying means, matching means, transforming means and PIN diode network are configured to form a portable integrated GaAs HBT switching power amplifier.

Claim 20

A high efficiency multiple power level power amplifier comprising: a first GaAs HBT having a base, a collector and an emitter; a second GaAs HBT having a base, a collector and an emitter; an interstage impedance matching network having an input coupled to the collector of the first GaAs HBT and having an output coupled to the base of the second GaAs HBT; a ground point; a third GaAs HBT having a base, a collector and an emitter, the emitter of the third GaAs HBT being coupled to the ground point; a resistor having a first end and a second end, the first end being coupled to the collector of the third GaAs HBT; a PIN diode network having an input coupled to the collector of the second GaAs HBT and having an output electrically coupled to the second end of the resistor; and an impedance transformation network having an input coupled to the input of the interstage impedance matching network and further having an output coupled to the output of the PIN diode network.

Claim 21

A high efficiency multiple power level power amplifier comprising: a first GaAs HBT having a base, a collector and an emitter; a second GaAs HBT having a base, a collector and an emitter; an interstage impedance matching network having an input coupled to the collector of the first GaAs HBT and having an output coupled to the base of the second GaAs HBT; a ground point; a third GaAs HBT having a base, a collector and an emitter, the emitter of the third GaAs HBT being coupled to the ground point; a resistor having a first end and a second end, the first end being coupled to the collector of the third GaAs HBT; a PIN diode network having an input coupled to the collector of the second GaAs HBT and having an output electrically coupled to the second end of the resistor; and an impedance transformation network having an input coupled to the input of the interstage impedance matching network and further having an output coupled to the output of the PIN diode network.

Claim 22

The high efficiency multiple power level power amplifier according to claim 14 further comprising an input stage impedance matching network having a signal input node, a ground node, an output node and a bias node, wherein the output node is coupled to the base of the first GaAs HBT.

Claim 23

The high efficiency multiple power level power amplifier according to claim 15 further comprising a first cascoded current mirror bias network coupled to the bias node of the input stage impedance matching network.

Claim 24

The high efficiency multiple power level power amplifier according to claim 16 further comprising a second cascoded current mirror bias network coupled to the base of the second GaAs HBT.

Claim 25

The high efficiency multiple power level power amplifier according to claim 17 further comprising an output stage impedance matching network having a signal input and a signal output, wherein the signal input is coupled to the collector of the second GaAs HBT.

Claim 26

The high efficiency multiple power level power amplifier according to claim 14 wherein the third GaAs HBT is configured to selectively enable and disable the PIN diode network such that a first impedance level can be set for the interstage impedance matching network when the PIN diode network is disabled and further such that the impedance transformation network can interact with the interstage impedance matching network when the PIN diode network is enabled to set a second impedance level for the interstage matching network.

Claim 29

The method of claim 20 further comprising the step of inactivating the PIN diode switching network to disengage the at least one impedance transformation network from the multistage RF power amplifier such that the multistage RF power amplifier is capable of generating an output signal having a power level that is limited by the matching network between each amplifier stage.