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US6353906B1
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Testing synchronization circuitry using digital simulation
Assignee: Bell Semiconductor LLC
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Filing: 1998-04-01
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Granted: 2002-03-05
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Expires: 2018-04-01
Abstract
Abstract To vigorously test synchronization logic and protocols in a digital circuit design, a synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time exhibited in actual circuits. The synchronization logic model is inserted into a software description of the design so that simulation will reveal faulty assumptions in the synchronization protocol. Additionally, where a non-synchronized signal crosses from one clock domain to another clock domain in an asynchronous digital design, a transition on the non-synchronized signal triggers an "X" value window on the signal for a selected period relative to the receiving clock period, so that simulation will fail if the receiving logic samples the signal value during the "X" value window. These techniques aid in effective testing of the design.
Inventors
- 👤 Michael B. Smith
- 👤 Michael J. Tresidder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
104 words
A method for use in testing an asynchronous digital design in which a non-synchronized signal crosses from a first clock domain to a second clock domain, the method comprising the steps of: responsive to a logic state transition on the non-synchronized signal from a first logic state to a second logic state, forcing the non-synchronized signal value to an “X” value, thereby starting an X value window; monitoring the synchronization clock signal during the X value window; and then changing the non-synchronized signal value to the second logic state, thereby terminating the X value window, at a time responsive to the synchronization clock signal.
Claim 2
Independent Claim
104 words
A method for use in testing an asynchronous digital design in which a non-synchronized signal crosses from a first clock domain to a second clock domain, the method comprising the steps of: responsive to a logic state transition on the non-synchronized signal from a first logic state to a second logic state, forcing the non-synchronized signal value to an “X” value, thereby starting an X value window; monitoring the synchronization clock signal during the X value window; and then changing the non-synchronized signal value to the second logic state, thereby terminating the X value window, at a time responsive to the synchronization clock signal.
Claim 3
Dependent Claim
38 words
A method according to claim 1 wherein said changing step includes changing the non-synchronized signal value to the second logic state, thereby terminating the X value window, in response to a next edge of the synchronization clock signal.
Claim 4
Dependent Claim
37 words
A method according to claim 1 wherein said changing step includes changing the non-synchronized signal value to the second logic state, thereby terminating the X value window, after at least one cycle of the synchronization clock signal.
Claim 5
Dependent Claim
30 words
A method according to claim 1 including selecting the X value window duration so as to ensure compliance with predetermined timing constraints of receiving logic in the second clock domain.
Claim 6
Dependent Claim
116 words
A behavioral model for forming an output signal for use in simulating an asynchronous digital design in which a non-synchronized signal crosses from a first clock domain to a second clock domain, the model comprising: means for intercepting and monitoring the non-synchronized signal; means for assigning an initial value of the non-synchronized signal as an initial value of the output signal; means for assigning an “X” simulation value to the output signal in response to a transition on the non-synchronized signal from the initial state to a complement state; and means for assigning the complement state of the non-synchronized signal to the output signal after a delay time responsive to the second clock domain clock signal.
Claim 7
Dependent Claim
116 words
A behavioral model for forming an output signal for use in simulating an asynchronous digital design in which a non-synchronized signal crosses from a first clock domain to a second clock domain, the model comprising: means for intercepting and monitoring the non-synchronized signal; means for assigning an initial value of the non-synchronized signal as an initial value of the output signal; means for assigning an “X” simulation value to the output signal in response to a transition on the non-synchronized signal from the initial state to a complement state; and means for assigning the complement state of the non-synchronized signal to the output signal after a delay time responsive to the second clock domain clock signal.
Claim 8
Dependent Claim
25 words
A behavioral model according to claim 5 wherein the delay time is selected as at least one cycle of the second clock domain clock signal.
Claim 9
Independent Claim
101 words
A method of introducing a simulated synchronization timing error into a simulated circuit running in a first clock domain to determine whether the simulated circuit is fault tolerant to the simulated synchronization timing error, where the simulated synchronization timing error is of a type that is created when a signal from a second clock domain is synchronized to the first clock domain and the signal is input to the simulated circuit, the method comprising the additional step of introducing a timing error at random times during the synchronization of the signal from the second clock domain to the first clock domain.
Claim 10
Independent Claim
101 words
A method of introducing a simulated synchronization timing error into a simulated circuit running in a first clock domain to determine whether the simulated circuit is fault tolerant to the simulated synchronization timing error, where the simulated synchronization timing error is of a type that is created when a signal from a second clock domain is synchronized to the first clock domain and the signal is input to the simulated circuit, the method comprising the additional step of introducing a timing error at random times during the synchronization of the signal from the second clock domain to the first clock domain.
Claim 11
Dependent Claim
17 words
The method of claim 7 , wherein the timing error further comprises one additional first clock cycle.
Claim 12
Dependent Claim
53 words
The method of claim 7 , wherein the timing error further comprises setting the signal to an X value for a first X window that initiates at a leading edge of the signal after synchronization and also for a second X window that initiates at a trailing edge of the signal after synchronization.
Claim 13
Dependent Claim
31 words
The method of claim 9 , wherein both the first X window and the second X window have an equal duration that is no less than a single first clock cycle.
Claim 14
Dependent Claim
52 words
The method of claim 9 , wherein the first X window terminates with a next occurrence of a first clock cycle edge following initiation of the first X window, add the second X window terminates with a next occurrence of a first clock cycle edge following initiation of the second X window.
Claim 15
Independent Claim
103 words
A method of introducing a simulated synchronization timing error into a simulated circuit running in a first clock domain to determine whether the simulated circuit is fault tolerant to the simulated synchronization timing error, where the simulated synchronization timing error is of a type that is created when a signal from a second clock domain is synchronized to the first clock domain and the signal is input to the simulated circuit, the method comprising the additional step of introducing one additional first clock cycle at random times during the synchronization of the signal from the second clock domain to the first clock domain.
Claim 16
Independent Claim
103 words
A method of introducing a simulated synchronization timing error into a simulated circuit running in a first clock domain to determine whether the simulated circuit is fault tolerant to the simulated synchronization timing error, where the simulated synchronization timing error is of a type that is created when a signal from a second clock domain is synchronized to the first clock domain and the signal is input to the simulated circuit, the method comprising the additional step of introducing one additional first clock cycle at random times during the synchronization of the signal from the second clock domain to the first clock domain.
Claim 17
Independent Claim
135 words
A method of introducing a simulated synchronization timing error into a simulated circuit running in a first clock domain to determine whether the simulated circuit is fault tolerant to the simulated synchronization timing error, where the simulated synchronization timing error is of a type that is created when a signal from a second clock domain is synchronized to the first clock domain and the signal is input to the simulated circuit, the method comprising the additional step of setting the signal to an X value for a first X window that initiates at a leading edge of the signal after synchronization and also for a second X window that initiates at a trailing edge of the signal after synchronization during the synchronization of the signal from the second clock domain to the first clock domain.
Claim 18
Independent Claim
135 words
A method of introducing a simulated synchronization timing error into a simulated circuit running in a first clock domain to determine whether the simulated circuit is fault tolerant to the simulated synchronization timing error, where the simulated synchronization timing error is of a type that is created when a signal from a second clock domain is synchronized to the first clock domain and the signal is input to the simulated circuit, the method comprising the additional step of setting the signal to an X value for a first X window that initiates at a leading edge of the signal after synchronization and also for a second X window that initiates at a trailing edge of the signal after synchronization during the synchronization of the signal from the second clock domain to the first clock domain.
Claim 19
Dependent Claim
31 words
The method of claim 13 , wherein both the first X window and the second X window have an equal duration that is no less than a single first clock cycle.
Claim 20
Dependent Claim
52 words
The method of claim 13 , wherein the first X window terminates with a next occurrence of a first clock cycle edge following initiation of the first X window, and the second X window terminates with a next occurrence of a first clock cycle edge following initiation of the second X window.
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USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 2005-03-04 | 2005-09-03 | 2006-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-04 | 2009-09-03 | 2010-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-04 | 2013-09-03 | 2014-03-05 | $7700.00 | Window Closed / Lapsed |