US6347294B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Upgradeable highly integrated embedded CPU system
Assignee: Twitter Inc
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Filing: 1998-09-22
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Granted: 2002-02-12
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Expires: 2018-09-22
Abstract
Abstract A system and method in accordance with the present invention provides for an embedded CPU system which is upgradeable through the use of an external CPU which can be utilized therewith. In a first aspect, the embedded CPU system includes a CPU and a plurality of devices which are accessible by the CPU, via a device control register bus. The embedded CPU system includes logic coupled to the device control register bus for allowing access to the devices within the embedded CPU system by an external CPU. In a preferred embodiment the present invention provides a highly integrated set top box controller with a processor performance that services the low-end with the added advantage of additional performance with the EMCPU operating as an I/O assist processor to the EXCPU. When the EXCPU operates as the primary processor these two processors serve as a high end set top box controller. A system and method in accordance with the present invention can also preserve much of the software programming model when migrating from a low end processor set top box controller to a higher end solution. A system and method in accordance with the present invention also offers a choice of preserving much of the existing software investment by allowing different processor architectures to function as the EXCPU.
Inventors
- 👤 Alan Jay Booker
- 👤 William Robert Lee
- 👤 Neil David Miles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:00
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
115 words
An embedded central processing unit (EMCPU) system comprising: a CPU subsystem, the CPU subsystem comprising an embedded CPU and on-chip memory (OCM) coupled to the embedded CPU, wherein the OCM reduces memory fetches for instruction execution; a plurality of devices; a bus coupled to the plurality of devices; wherein the bus is a device control register (DCR) bus; and DCR extension (DCRX) logic coupled to the DCR bus for allowing access to the devices by an external CPU (EXCPU) via the DCR bus, wherein the DCRX logic includes arbitration control logic for controlling access to the DCR bus by the EMCPU and the EXCPU, and DCRX control logic and registers for controlling the DCR bus.
Claim 2
Dependent Claim
115 words
An embedded central processing unit (EMCPU) system comprising: a CPU subsystem, the CPU subsystem comprising an embedded CPU and on-chip memory (OCM) coupled to the embedded CPU, wherein the OCM reduces memory fetches for instruction execution; a plurality of devices; a bus coupled to the plurality of devices; wherein the bus is a device control register (DCR) bus; and DCR extension (DCRX) logic coupled to the DCR bus for allowing access to the devices by an external CPU (EXCPU) via the DCR bus, wherein the DCRX logic includes arbitration control logic for controlling access to the DCR bus by the EMCPU and the EXCPU, and DCRX control logic and registers for controlling the DCR bus.
Claim 3
Dependent Claim
13 words
The EMCPU system of claim 1 wherein the logic includes bus extension logic.
Claim 4
Dependent Claim
21 words
The EMCPU system of claim 1 wherein the embedded CPU subsystem further comprises: an interrupt controller coupled to the embedded CPU.
Claim 5
Dependent Claim
19 words
The EMCPU system of claim 1 wherein the EMCPU system includes a peripheral subsystem coupled to the CPU subsystem.
Claim 6
Dependent Claim
17 words
The EMCPU system of claim 4 wherein the peripheral subsystem includes a general purpose I/O (GPIO) device.
Claim 7
Dependent Claim
20 words
The EMCPU system of claim 5 wherein a first low latency path is provided from the EMCPU to the EXCPU.
Claim 8
Dependent Claim
16 words
The EMCPU system of claim 6 wherein the EMCPU and EXCPU share a common memory interface.
Claim 9
Dependent Claim
20 words
The EMCPU system of claim 7 wherein the shared memory is utilized for communication between the EXCPU and the EMCPU.
Claim 10
Dependent Claim
55 words
The EMCPU system of claim 6 wherein the first low latency path comprises: means for causing the EMCPU to write to the GPIO device; means for causing the GPIO device to drive an output of the EMCPU system; and means responsive to the GPIO device causing means for receiving an interrupt input by the EXCPU.
Claim 11
Dependent Claim
20 words
The EMCPU system of claim 9 wherein a second low latency path is provided from the EXCPU to the EMCPU.
Claim 12
Dependent Claim
69 words
The EMCPU system of claim 10 , wherein the second low latency path comprises: means for causing the EXCPU to write to the DCRX logic; means responsive to the EXCPU causing means for asserting an interrupt to the interrupt controller; means responsive to the interrupt controller asserting means for asserting the interrupt to the CPU subsystem; and means for causing the CPU subsystem to branch to a system table.
Claim 13
Dependent Claim
148 words
A highly integrated set top box (HISTB) comprising: a CPU subsystem, the CPU subsystem comprising an embedded CPU (EMCPU) and on-chip memory (OCM) coupled to the EMCPU wherein the OCM reduces memory fetches for instruction execution; an MPEG subsystem; a memory subsystem; a peripheral subsystem; at least one bus for allowing communication between the CPU subsystem, the MPEG subsystem, the memory subsystem and the peripheral subsystem; a device control register (DCR) bus for coupling the CPU subsystem, the MPEG subsystem, and the memory subsystem; and DCR extension (DCRX) logic coupled to the DCR bus for allowing access to the CPU subsystem, memory subsystem and the MPEG subsystem by an external CPU (EXCPU) via the DCR bus, wherein the DCRX logic includes arbitration control logic for controlling access to the DCR bus by the EMCPU and the EXCPU, and DCRX control logic and registers for controlling the DCR bus.
Claim 14
Dependent Claim
148 words
A highly integrated set top box (HISTB) comprising: a CPU subsystem, the CPU subsystem comprising an embedded CPU (EMCPU) and on-chip memory (OCM) coupled to the EMCPU wherein the OCM reduces memory fetches for instruction execution; an MPEG subsystem; a memory subsystem; a peripheral subsystem; at least one bus for allowing communication between the CPU subsystem, the MPEG subsystem, the memory subsystem and the peripheral subsystem; a device control register (DCR) bus for coupling the CPU subsystem, the MPEG subsystem, and the memory subsystem; and DCR extension (DCRX) logic coupled to the DCR bus for allowing access to the CPU subsystem, memory subsystem and the MPEG subsystem by an external CPU (EXCPU) via the DCR bus, wherein the DCRX logic includes arbitration control logic for controlling access to the DCR bus by the EMCPU and the EXCPU, and DCRX control logic and registers for controlling the DCR bus.
Claim 15
Dependent Claim
17 words
The HISTB of claim 12 wherein the DCR bus is implemented as a daisy chained DCR ring.
Claim 16
Dependent Claim
28 words
The HISTB of claim 12 wherein the DCR extension (DCRX) logic which provides a path for the EMCPU and EXCPU to access registers attached to the DCR bus.
Claim 17
Dependent Claim
19 words
The HISTB of claim 12 wherein the CPU subsystem further comprises: an interrupt controller coupled to the embedded CPU.
Claim 18
Dependent Claim
47 words
The HISTB of claim 15 wherein the memory subsystem comprises: a DMA controller coupled to the CPU subsystem; a cross bar switch coupled to DMA controller; a DRAM/SRAM interface coupled to the memory interface and the crossbar switch; and an SRAM interface coupled to the crossbar switch.
Claim 19
Dependent Claim
30 words
The HISTB of claim 14 wherein the at least one bus includes: first and second buses for allowing communications between the CPU subsystem, the memory subsystem and the MPEG subsystems.
Claim 20
Dependent Claim
44 words
The HISTB of claim 17 wherein the MPEG subsystem comprises: an MPEG transport demultiplexer coupled to one of the first and second buses; an MPEG audio decoder coupled to the MPEG transport demultiplexer; and an MPEG video decoder coupled to the MPEG transport demultiplexer.
Claim 21
Dependent Claim
16 words
The HISTB of claim 18 wherein the peripheral subsystem includes a general purpose I/O (GPIO) device.
Claim 22
Dependent Claim
32 words
The HISTB of claim 19 wherein the at least one bus includes an OPB bus which allows for communication between the peripheral subsystem and the EMCPU subsystem, memory subsystem and MPEG subsystem.
Claim 23
Dependent Claim
19 words
The HISTB of claim 20 wherein a first low latency path is provided from the EMCPU to the EXCPU.
Claim 24
Dependent Claim
54 words
The HISTB of claim 21 wherein the first low latency path comprises: means for causing the CPU subsystem to write to the GPIO device; means for causing the GPIO device to drive an output of the HISTB; and means responsive to the GPIO device causing means for receiving an interrupt input by the EXCPU.
Claim 25
Dependent Claim
19 words
The HISTB of claim 22 wherein a second low latency path is provided from the EXCPU to the EMCPU.
Claim 26
Dependent Claim
68 words
The HISTB of claim 23 wherein the second low latency path comprises: means for causing the EXCPU to write to the DCRX register space; means responsive to the EXCPU causing means for asserting an interrupt to the interrupt controller; means responsive to the interrupt controller asserting means for asserting the interrupt to the CPU subsystem; and means for causing the CPU subsystem to branch to a system table.
Claim 27
Dependent Claim
19 words
The HISTB of claim 24 which includes a dedicated signal for providing access to the logic by the EXCPU.
Claim 28
Dependent Claim
70 words
The HISTB of claim 25 wherein the arbitration control logic receives arbitration signals from the memory controller and the EXCPU, the DCRX control logic receives arbitration information from the arbitration control logic and determines the states of the signals for the DCR bus; and wherein the DCRX logic further comprises a plurality of multiplexers for allowing an external bus and the DCR bus to be controlled by the DCRX logic.
Claim 29
Dependent Claim
19 words
The HISTB of claim 26 which includes a staged power on reset mechanism for the EXCPU and the EMCPU.
Claim 30
Dependent Claim
48 words
The HISTB of claim 27 wherein the staged power on reset mechanism comprises: means for holding the EMCPU in reset until the EXCPU is out of reset and initialized; and means for releasing the reset of the EMCPU responsive to the EXCPU being out of reset and initialized.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-11 | 2005-08-13 | 2006-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-11 | 2009-08-13 | 2010-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-11 | 2013-08-13 | 2014-02-12 | $7700.00 | Window Closed / Lapsed |