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US6345359B1
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In-line decryption for protecting embedded software
Assignee: Raytheon Co
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Filing: 1997-11-14
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Granted: 2002-02-05
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Expires: 2017-11-14
Abstract
Abstract An in-line decryptor is employed to decrypt software (program instructions) transferred from a read only memory to a central processing unit. The in-line decryptor comprises a keystream generator that contains a cryptographic algorithm coupled to a memory that stores cryptographic keys. A combining function implemented using two substitution functions and two XOR functions generates an output keystream of the keystream generator. The decryptor uses the cryptographic algorithm to initialize a variation of a one time pad cryptosystem. Using a number of relatively short pseudorandom sequences and a simple combining function, a much longer address-dependent pseudorandom sequence is created. This sequence is used to decrypt the encrypted software in real time on an instruction-by-instruction basis.
Inventors
- 👤 Mark E. Bianco
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:39
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1408; G06F21/00; G06F21/10; G06F21/12; G06F21/121; G06F21/123; G06F21/70; G06F21/71; G06F21/72; H; H04; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L2209/00; H04L2209/12
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
111 words
Apparatus for protecting embedded software, said apparatus comprising: a central processing unit having a unidirectional address bus, bidirectional data bus, and a control bus; a read only memory coupled to the central processing unit by way of the busses; and wherein individual encrypted program instructions are transferred between the read only memory and the central processing unit by way of the busses; and a key-dependent in-line decryptor disposed in-line with the data bus for decrypting the individual encrypted program instructions that are transferred from the read only memory to the central processing unit on an instruction-by-instruction basis, which decrypted program instructions are executed by the central processing unit without interim storage.
Claim 2
Dependent Claim
111 words
Apparatus for protecting embedded software, said apparatus comprising: a central processing unit having a unidirectional address bus, bidirectional data bus, and a control bus; a read only memory coupled to the central processing unit by way of the busses; and wherein individual encrypted program instructions are transferred between the read only memory and the central processing unit by way of the busses; and a key-dependent in-line decryptor disposed in-line with the data bus for decrypting the individual encrypted program instructions that are transferred from the read only memory to the central processing unit on an instruction-by-instruction basis, which decrypted program instructions are executed by the central processing unit without interim storage.
Claim 3
Dependent Claim
56 words
The apparatus of claim 1 wherein the in-line decryptor comprises: a bus control interface having an input coupled to the control bus; a keystream generator having an input coupled to the address bus; and a summing device that is disposed in-line with the data bus prior to the bus control interface of the central processing unit.
Claim 4
Dependent Claim
104 words
The apparatus of claim 1 wherein the in-line decryptor operates in a read only memory read mode, wherein when the central processing unit reads program instructions from the read only memory, the in-line decryptor uses the address of each instruction as an input to the keystream generator, which implements a cryptographic process that produces a pseudorandom word of the same width as the data bus, and wherein the pseudorandom word is then bitwise exclusive-or'd with the encrypted instruction from the read only memory via the data bus to decrypt the instruction, which is then output to the central processing unit data bus for execution.
Claim 5
Dependent Claim
62 words
The apparatus of claim 1 further comprising an address decoder coupled to the address bus and the keystream generator for disabling the output of the keystream generator when the central processing unit attempts to read program instructions from addresses or address segments allocated to non-encrypted instructions, which instructions pass through the in-line decryptor to the central processing unit data bus without modification.
Claim 6
Dependent Claim
20 words
The apparatus of claim 1 wherein the central processing unit and in-line decryptor are monolithically integrated on a single die.
Claim 7
Dependent Claim
20 words
The apparatus of claim 1 wherein the central processing unit and in-line decryptor are integrated in a single multi-chip module.
Claim 8
Dependent Claim
19 words
The apparatus of claim 1 wherein the central processing unit and in-line decryptor are encased in a tamper-resistant material.
Claim 9
Dependent Claim
22 words
The apparatus of claim 1 further comprising: a random access memory coupled to the central processing unit by way of the busses.
Claim 10
Dependent Claim
65 words
The apparatus of claim 8 wherein the in-line decryptor operates in a random access memory write mode, wherein when the central processing unit attempts to write data to the random access memory, the bus control interface in the in-line decryptor decodes control signals to allow data from the central processing unit data bus to pass through the in-line decryptor to the data bus without modification.
Claim 11
Dependent Claim
62 words
The apparatus of claim 8 wherein the in-line decryptor operates in a random access memory read mode, wherein when the central processing unit attempts to read data from the random access memory, the bus control interface decodes control signals to allow the data on system data bus to pass through the in-line decryptor to the central processing unit data bus without modification.
Claim 12
Dependent Claim
54 words
The apparatus of claim 1 wherein the in-line decryptor comprises: a keystream generator; a memory for storing cryptographic keys; first and second substitution functions that contain pseudorandom data generated by a cryptographic algorithm; and first and second XOR functions that respectively perform a bitwise XOR of two n-bit inputs to produce an n-bit output.
Claim 13
Dependent Claim
42 words
The apparatus of claim 11 wherein each substitution function is statistically unbiased and nonlinear, and the functions interact with the XOR functions in such a manner as to ensure that the output of the keystream generator is also statistically unbiased and nonlinear.
Claim 14
Dependent Claim
17 words
The apparatus of claim 12 wherein the substitution functions are implemented as substitution tables using RAM devices.
Claim 15
Dependent Claim
14 words
The apparatus of claim 11 wherein the cryptographic algorithm comprises a symmetric cryptographic algorithm.
Claim 16
Dependent Claim
16 words
The apparatus of claim 14 wherein the symmetric cryptographic algorithm comprises a Data Encryption Standard algorithm.
Claim 17
Dependent Claim
14 words
The apparatus of claim 11 wherein the cryptographic algorithm comprises an asymmetric cryptographic algorithm.
Claim 18
Dependent Claim
14 words
The apparatus of claim 16 wherein the asymmetric cryptographic algorithm comprises a Rivest-Shamir-Adleman algorithm.
Claim 19
Dependent Claim
28 words
The apparatus of claim 11 wherein the substitution functions are implemented using nonvolatile memory devices that are programmed with statistically unbiased random data generated by a nondeterministic process.
Claim 20
Dependent Claim
36 words
The apparatus of claim 18 wherein the nonvolatile memory devices are selected from the group comprising read only memories, programmable read only memories, electrically eraseable programmable read only memories, and ultraviolet radiation programmable read only memories.
Claim 21
Dependent Claim
15 words
The apparatus of claim 18 wherein the nonvolatile memory devices are programmed using thermal noise.
Claim 22
Dependent Claim
15 words
The apparatus of claim 18 wherein the nonvolatile memory devices are programmed using atmospheric noise.
Claim 23
Dependent Claim
106 words
Apparatus for protecting embedded software, said apparatus comprising: a central processing unit having a unidirectional address bus, bidirectional data bus, and a control bus; a storage device coupled to the central processing unit by way of the busses; and wherein encrypted program instructions are transferred between the storage device and the central processing unit by way of the busses; and an in-line decryptor disposed in-line with the data bus for decrypting the individual encrypted program instructions that are transferred from the storage device to the central processing unit on an instruction-by-instruction basis, which decrypted program instructions are executed by the central processing unit without interim storage.
Claim 24
Dependent Claim
106 words
Apparatus for protecting embedded software, said apparatus comprising: a central processing unit having a unidirectional address bus, bidirectional data bus, and a control bus; a storage device coupled to the central processing unit by way of the busses; and wherein encrypted program instructions are transferred between the storage device and the central processing unit by way of the busses; and an in-line decryptor disposed in-line with the data bus for decrypting the individual encrypted program instructions that are transferred from the storage device to the central processing unit on an instruction-by-instruction basis, which decrypted program instructions are executed by the central processing unit without interim storage.
Claim 25
Dependent Claim
54 words
The apparatus of claim 22 wherein the in-line decryptor comprises: a keystream generator; a memory for storing cryptographic keys; first and second substitution functions that contain pseudorandom data generated by the cryptographic algorithm; and first and second XOR functions that respectively perform a bitwise XOR of two n-bit inputs to produce an n-bit output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-02-04 | 2005-08-06 | 2006-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-04 | 2009-08-06 | 2010-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-04 | 2013-08-06 | 2014-02-05 | $7700.00 | Window Closed / Lapsed |