Patent US6345321B1 successfully refreshed from Google Patents.
US6345321B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple-mode memory component
Assignee: Intel Corp
•
Filing: 2000-05-24
•
Granted: 2002-02-05
•
Expires: 2020-05-24
Abstract
Abstract A memory component on a single integrated circuit includes a RAM, one or more configuration registers, and an associated controller. The behavior of the memory component, including selection from a number of different operating modes, is controllable via configuration register mode bits. The various modes include several transfer-length modes, where each mode corresponds to data transfers of a predetermined length. Based on the mode selection specified by the mode bits, the controller determines the length of the data transfers.
Inventors
- 👤 Daniel Litaize
- 👤 Jean-Claude Salinier
- 👤 Abdelaziz Mzoughi
- 👤 Fatima-Zahra Elkhlifi
- 👤 Mustapha Lalam
- 👤 Pascal Sainrat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:06
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0813; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1036
Claims Analysis
Total Claims: 60
Claim 1
Independent Claim
99 words
A memory component on a single integrated circuit having a plurality of pins for coupling to an external master, the memory component comprising: a storage subsystem having a plurality of storage locations; a plurality of configuration bits in at least one configuration register, the configuration bits specifying one of a plurality of modes including transfer-length modes corresponding to transfers of a mode-specific number of the storage locations between the storage subsystem and the external master; and control logic coupled to the storage subsystem and the configuration bits, the control logic executing the transfers in accordance with the configuration bits.
Claim 2
Dependent Claim
99 words
A memory component on a single integrated circuit having a plurality of pins for coupling to an external master, the memory component comprising: a storage subsystem having a plurality of storage locations; a plurality of configuration bits in at least one configuration register, the configuration bits specifying one of a plurality of modes including transfer-length modes corresponding to transfers of a mode-specific number of the storage locations between the storage subsystem and the external master; and control logic coupled to the storage subsystem and the configuration bits, the control logic executing the transfers in accordance with the configuration bits.
Claim 3
Dependent Claim
36 words
The memory component of claim 1 , wherein the number of the storage locations transferred between the storage subsystem and the external master is decoded based on the mode of operation specified by the configuration bits.
Claim 4
Dependent Claim
33 words
The memory component of claim 1 , wherein the number of unique transfer-lengths over all the modes is less than the number of storage locations transferred in a transfer of the maximum length.
Claim 5
Dependent Claim
20 words
The memory component of claim 3 , wherein the available transfer lengths include lengths of 2 and 8 addressable locations.
Claim 6
Dependent Claim
20 words
The memory component of claim 4 , wherein the available transfer lengths further include a length of 4 addressable locations.
Claim 7
Dependent Claim
20 words
The memory component of claim 3 , wherein the available transfer lengths include lengths of 16 bits and 64 bits.
Claim 8
Dependent Claim
19 words
The memory component of claim 6 , wherein the available transfer lengths further include a length of 32 bits.
Claim 9
Dependent Claim
20 words
The memory component of claim 3 , wherein the plurality of storage locations is implemented as dynamic random access memory.
Claim 10
Dependent Claim
23 words
The memory component of claim 1 , wherein the number of available transfer lengths is less than the length of the maximum transfer.
Claim 11
Dependent Claim
15 words
The memory component of claim 1 , wherein the plurality of pins is 51 .
Claim 12
Dependent Claim
42 words
The memory component of claim 1 , wherein the plurality of pins includes at least a first pin dedicated to an externally provided clock, and at least a second pin dedicated to data that is latched synchronous to the externally provided clock.
Claim 13
Dependent Claim
43 words
The memory component of claim 11 , further wherein at least a third pin is dedicated to a second externally provided clock, and at least at least a fourth pin dedicated to data that is latched synchronous to the second externally provided clock.
Claim 14
Dependent Claim
12 words
The memory component of claim 11 , further including additional data pins.
Claim 15
Dependent Claim
20 words
The memory component of claim 11 , wherein the plurality of storage locations is implemented as dynamic random access memory.
Claim 16
Dependent Claim
51 words
The memory component of claim 1 , wherein the plurality of pins includes a first subset of pins dedicated to externally provided clocks, and a second subset of respectively associated pins dedicated to data, wherein the data on the data pins is latched synchronous to the respectively associated externally provided clocks.
Claim 17
Dependent Claim
46 words
The memory component of claim 1 , further wherein the control logic is a slave to the external master, the control logic executing the transfers only when commanded by the external master, the configuration bits having been previously loaded at the command of the external master.
Claim 18
Dependent Claim
25 words
The memory component of claim 16 , wherein the transfer-length selected via the configuration bits is persistent across multiple transfers commanded by the external master.
Claim 19
Dependent Claim
20 words
The memory component of claim 16 , wherein the plurality of storage locations is implemented as dynamic random access memory.
Claim 20
Dependent Claim
109 words
The memory component of claim 1 , wherein the storage locations are physically organized as at least a two dimensional array, the array including a plurality of addressable locations in a first dimension, and a plurality of addressable locations in a second dimension, the storage subsystem having first dimension control inputs for accessing a block of locations corresponding to a particular first dimension address and second dimension control inputs for accessing a selected subset of the block of locations, the control logic generating the first and second dimension control inputs as a function of both an address provided by the external master and the configuration bits specified transfer-length mode.
Claim 21
Dependent Claim
21 words
The memory component of claim 19 , wherein the plurality of addressable locations in the first dimension is 2 16 .
Claim 22
Dependent Claim
23 words
The memory component of claim 19 , wherein the plurality of addressable locations in the first dimension is at least 2 16 .
Claim 23
Dependent Claim
22 words
The memory component of claim 19 , wherein each addressable location in the first dimension corresponds to a block of 64 bits.
Claim 24
Dependent Claim
24 words
The memory component of claim 19 , wherein each addressable location in the first dimension corresponds to a block of at least 64 bits.
Claim 25
Dependent Claim
19 words
The memory component of claim 19 , wherein the plurality of addressable locations in the second dimension is 8.
Claim 26
Dependent Claim
21 words
The memory component of claim 19 , wherein the plurality of addressable locations in the second dimension is at least 8.
Claim 27
Dependent Claim
19 words
The memory component of claim 19 , wherein each addressable location in the second dimension corresponds to 8 bits.
Claim 28
Dependent Claim
21 words
The memory component of claim 19 , wherein each addressable location in the second dimension corresponds to at least 8 bits.
Claim 29
Dependent Claim
66 words
The memory component of claim 1 , further including: a first and second interface coupled to the control logic and to which a first and second number of the pins are respectively dedicated during normal operation, and wherein commands are received from the external master via the first interface and data transfers between the storage subsystem and the external master are performed via the second interface.
Claim 30
Dependent Claim
23 words
The memory component of claim 28 , wherein the data transfers between the storage subsystem and the external master are burst data transfers.
Claim 31
Dependent Claim
30 words
The memory component of claim 28 , wherein the transfers between the second interface and the external master are synchronized to a normally continuously operating externally provided data transfer clock.
Claim 32
Dependent Claim
21 words
The memory component of claim 30 , wherein the data transfer clock is asynchronous with other circuitry of the memory component.
Claim 33
Dependent Claim
25 words
The memory component of claim 30 , wherein the length of the transfers is determined by the control logic in accordance with the configuration bits.
Claim 34
Dependent Claim
25 words
The memory component of claim 28 , wherein the second interface comprises a plurality of bit-slices enabling the concurrent transfer of a plurality of bits.
Claim 35
Dependent Claim
15 words
The memory component of claim 33 , wherein the second interface is 8 bits wide.
Claim 36
Dependent Claim
27 words
The memory component of claim 33 , wherein the transfers between the second interface and the external master are synchronized to at least one data transfer clock.
Claim 37
Dependent Claim
21 words
The memory component of claim 35 , wherein each data transfer clock is asynchronous with other circuitry of the memory component.
Claim 38
Dependent Claim
19 words
The memory component of claim 35 , wherein the data transfer clock is externally provided to the memory component.
Claim 39
Dependent Claim
18 words
The memory component of claim 37 , wherein the externally provided data transfer clock is normally continuously operating.
Claim 40
Dependent Claim
25 words
The memory component of claim 38 , wherein the length of the transfers is determined by the control logic in accordance with the configuration bits.
Claim 41
Dependent Claim
25 words
The memory component of claim 37 , wherein the length of the transfers is determined by the control logic in accordance with the configuration bits.
Claim 42
Dependent Claim
20 words
The memory component of claim 40 , wherein the plurality of storage locations is implemented as dynamic random access memory.
Claim 43
Dependent Claim
26 words
The memory component of claim 33 , wherein the second interface is bi-directional and is used for both writes and reads commanded by the external master.
Claim 44
Dependent Claim
26 words
The memory component of claim 28 , wherein the second interface is bi-directional and is used for both writes and reads commanded by the external master.
Claim 45
Dependent Claim
38 words
The memory component of claim 28 , further including a third interface to which a third number of pins are dedicated during normal operation and wherein configuration data is received from the external master via the third interface.
Claim 46
Dependent Claim
20 words
The memory component of claim 28 , further wherein addresses are received from the external master via the first interface.
Claim 47
Dependent Claim
35 words
The memory component of claim 28 , wherein the second includes at least 1 pin dedicated to data being selectively transferred between the storage subsystem and the external master in accordance with the configuration bits.
Claim 48
Dependent Claim
24 words
The memory component of claim 46 , wherein the data transfer between the storage subsystem and the external matter is a burst data transfer.
Claim 49
Dependent Claim
20 words
The memory component of claim 46 , wherein the total number of pins dedicated to data being transferred is 8.
Claim 50
Dependent Claim
23 words
The memory component of claim 48 , wherein the data transfer between the storage subsystem and the external master is serial data transfer.
Claim 51
Dependent Claim
21 words
The memory component of claim 1 , wherein the plurality of configuration bits are organized in a plurality of configuration registers.
Claim 52
Dependent Claim
33 words
The memory component of claim 50 , wherein the number of unique transfer-lengths over all the modes is less than the number of storage locations transferred in a transfer of the maximum length.
Claim 53
Dependent Claim
45 words
The memory component of claim 50 , further wherein the control logic is slave to the external master, the control logic executing the transfers only when commanded by the external master, the configuration bits having been previously loaded at the command of the external master.
Claim 54
Dependent Claim
25 words
The memory component of claim 52 , wherein the transfer-length selected via the configuration bits is persistent across multiple transfers commanded by the external master.
Claim 55
Dependent Claim
20 words
The memory component of claim 53 , wherein the plurality of storage locations is implemented as dynamic random access memory.
Claim 56
Dependent Claim
66 words
The memory component of claim 50 , further including: a first and second interface coupled to the control logic and to which a first and second number of the pins are respectively dedicated during normal operation, and wherein commands are received from the external master via the first interface and data transfers between the storage subsystem and the external master are performed via the second interface.
Claim 57
Dependent Claim
30 words
The memory component of claim 55 , wherein the transfers between the second interface and the external master are synchronized to a normally continuously operating externally provided data transfer clock.
Claim 58
Dependent Claim
20 words
The memory component of claim 56 , wherein the plurality of storage locations is implemented as dynamic random access memory.
Claim 59
Dependent Claim
20 words
The memory component of claim 50 , wherein the plurality of storage locations is implemented as dynamic random access memory.
Claim 60
Dependent Claim
20 words
The memory component of claim 1 , wherein the plurality of storage locations is implemented as dynamic random access memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-04 | 2005-08-06 | 2006-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-04 | 2009-08-06 | 2010-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-04 | 2013-08-06 | 2014-02-05 | $7700.00 | Window Closed / Lapsed |