Processor for image-pixel signals derived from divided sections of image-sensing area of solid-type image sensor

Claim 2

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area, which is divided into a first section and a second section, of a solid-type image sensor, said signal processor comprising: an image-pixel signal reader that simultaneously and correspondingly reads two respective series of image-pixel signals line by line from said first section and said second section of said image-sensing area, a leading image-pixel signal of the image-pixel signals included in each line being farthest away from a boundary between said first section and said second section, a trailing image-pixel signal of the image-pixel signals included in each line being nearest to said boundary; and a regulator that correspondingly regulates respective differences between levels of the image-pixel signals in each line, derived from said first section, and corresponding image-pixel signals in each line, derived from said second section, so that a gradual reduction occurs, resulting in both levels of the trailing image-pixel signals, derived from said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel-signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, which is cyclically varied from a minimum value to a maximum value, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first and second sections on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 3

An image-pixel signal processor as set forth in claim 1 , wherein said first level-changer and said second level-changer comprise a first voltage-controlled amplifier and a second voltage-controlled amplifier, and a magnification factor of each voltage-controlled amplifier is controlled in accordance with a variation of an inputted control voltage, the inputted control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor.

Claim 4

The image-pixel signal processor of claim 2 , wherein said first level detector outputs a voltage signal (V 1st ) as the detected level of the image-pixel signal derived from said first section, said second level detector outputs a voltage signal (V 2nd ) as the detected level of the image-pixel signal derived from said second section, and said calculator outputs a voltage signal (V 1st -V 2nd ) as the differential level between the levels of the voltage signals outputted from said first level-changer and said second level- changer, respective control voltages (VC 1st and VC 2nd ) of said first voltage-controlled amplifier and said second voltage-controlled amplifier being defined as follows: VC 1st =(1−WF)V 1st +WF*V 2nd VC 2nd =(1−WF)V 2nd +WF*V 1st where WF represents the weight-factor (0≦WF≦1).

Claim 5

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area, vertically divided into a first section and a second section, of a solid-type image sensor, a plurality of image-pixel signals being produced in a matrix arrangement on each of said first section and said second section, said signal processor comprising: an image-pixel signal reader that reads respective series of image-pixel signals, from a leading line of said first section and said second section, by vertically transferring said plurality of image-pixel signals in a line by line succession, and by horizontally transferring a vertically-transferred leading line of said plurality of image-pixel signals, a leading image-pixel signal of the image-pixel signals included in each line being farthest from a vertical boundary between said first section and said second section, a trailing image-pixel signal of the image-pixel signals included in each line being nearest to said vertical boundary; and a regulator that correspondingly regulates respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, so that a gradual reduction occurs, resulting in both levels of the trailing image-pixel signals, derived from said first and second sections, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image- pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier multiplying the differential level by a weight-factor, said weight-factor being cyclically varied from a minimum value to a maximum value in accordance with a series of clock pulses, on the basis of which the vertical transfer of the plurality of image-pixel signals is carried out in each of said first section and said second section, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first section and said second section on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 6

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area, vertically divided into a first section and a second section, of a solid-type image sensor, a plurality of image-pixel signals being produced in a matrix arrangement on each of said first section and said second section, said signal processor comprising: an image-pixel signal reader that reads respective series of image-pixel signals, from a leading line of said first section and said second section, by vertically transferring said plurality of image-pixel signals in a line by line succession, and by horizontally transferring a vertically-transferred leading line of said plurality of image-pixel signals, a leading image-pixel signal of the image-pixel signals included in each line being farthest from a vertical boundary between said first section and said second section, a trailing image-pixel signal of the image-pixel signals included in each line being nearest to said vertical boundary; and a regulator that correspondingly regulates respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, so that a gradual reduction occurs, resulting in both levels of the trailing image-pixel signals, derived from said first and second sections, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image- pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier multiplying the differential level by a weight-factor, said weight-factor being cyclically varied from a minimum value to a maximum value in accordance with a series of clock pulses, on the basis of which the vertical transfer of the plurality of image-pixel signals is carried out in each of said first section and said second section, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first section and said second section on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 7

An image-pixel signal processor as set forth in claim 4 , wherein said first level-changer and said second level-changer comprise a first voltage-controlled amplifier and a second voltage-controlled amplifier, and a magnification factor of each voltage-controlled amplifier is controlled in accordance with a variation of an inputted control voltage, the inputted control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor.

Claim 8

The image-pixel signal processor of claim 5 , wherein said first level detector outputs a voltage signal (V 1st ) as the detected level of the image-pixel signal derived from said first section, said second level detector outputs a voltage signal (V 2nd ) as the detected level of the image-pixel signal derived from said second section, and said calculator outputs a voltage signal (V 1st -V 2nd ) as the differential level between the levels of the voltage signals outputted from said first level-changer and said second level-changer, the respective control voltages (VC 1st and VC 2nd ) of said first voltage-controlled amplifier and said second voltage-controlled amplifier being defined as follows: VC 1st =(1−WF)V 1st +WF*V 2nd VC 2nd =(1−WF)V 2nd +WF*V 1st where WF represents the weight-factor (0≦WF≦1).

Claim 9

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area, horizontally divided into a first section and a second section, of a solid-type image sensor, a plurality of image-pixel signals being produced in a matrix arrangement on each o said first section and said second section, said signal processor comprising: an image-pixel signal reader that reads respective series of image-pixel signals, from a leading line of said first section and said second section, by vertically transferring said plurality of image-pixel signals in a line by line succession, and by horizontally transferring a vertically transferred leading line of said plurality of image-pixel signals, a leading series of said plurality of image-pixel signals, first to be horizontally transferred from said first section and said second section, being farthest from a horizontal boundary between said first section and said second section, a trailing series of said plurality of image-pixel signals, last to be horizontally transferred from said first second section and said second section, being nearest to said horizontal boundary; and a regulator that correspondingly regulates respective differences between levels, represented by the image-pixel signals in respective lines, derived from said first section, and corresponding levels, represented by the image-pixel signals in respective lines, derived from said second section, so that a gradual reduction occurs, resulting in both levels, represented by the image-pixel signals in the trailing lines of said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, said weight-factor being cyclically varied from a minimum value to a maximum value in accordance with a series of clock pulses, on the basis of which the horizontal transfer of the plurality of image-pixel signals is carried out in each of said first section and said second section, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first and second sections on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 10

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area, horizontally divided into a first section and a second section, of a solid-type image sensor, a plurality of image-pixel signals being produced in a matrix arrangement on each o said first section and said second section, said signal processor comprising: an image-pixel signal reader that reads respective series of image-pixel signals, from a leading line of said first section and said second section, by vertically transferring said plurality of image-pixel signals in a line by line succession, and by horizontally transferring a vertically transferred leading line of said plurality of image-pixel signals, a leading series of said plurality of image-pixel signals, first to be horizontally transferred from said first section and said second section, being farthest from a horizontal boundary between said first section and said second section, a trailing series of said plurality of image-pixel signals, last to be horizontally transferred from said first second section and said second section, being nearest to said horizontal boundary; and a regulator that correspondingly regulates respective differences between levels, represented by the image-pixel signals in respective lines, derived from said first section, and corresponding levels, represented by the image-pixel signals in respective lines, derived from said second section, so that a gradual reduction occurs, resulting in both levels, represented by the image-pixel signals in the trailing lines of said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, said weight-factor being cyclically varied from a minimum value to a maximum value in accordance with a series of clock pulses, on the basis of which the horizontal transfer of the plurality of image-pixel signals is carried out in each of said first section and said second section, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first and second sections on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 11

An image-pixel signal processor as set forth in claim 7 , wherein said first level-changer and said second level-changer comprise a first voltage-controlled amplifier and a second voltage-controlled amplifier, and a magnification factor of each voltage-controlled amplifier is controlled in accordance with a variation of an inputted control voltage, the inputted control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor.

Claim 12

The image-pixel signal processor of claim 8 , wherein said first level detector outputs a voltage signal (V 1st ) as the detected level of the image-pixel signal derived from said first section, said second level detector outputs a voltage signal (V 2nd ) as the detected level of the image-pixel signal derived from said second section, and said calculator outputs a voltage signal (V 1st -V 2nd ) as the differential level between the levels of the voltage signals outputted from said first level-changer and said second level-changer, respective control voltages (VC 1st and VC 2nd ) of said first voltage-controlled amplifier and said second voltage-controlled amplifier being defined as follows: VC 1st =(1−WF)V 1st +WF*V 2nd VC 2nd =(1−WF)V 2nd +WF*V 1st where WF represents the weight-factor (0≦WF≦1).

Claim 13

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area of a solid-type image sensor, which is constructed by combining at least two small-sized solid-type image sensors with each other such that said image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of said small-sized solid-type image sensors, respectively, said signal processor comprising: an image-pixel signal reader that simultaneously and correspondingly reads two respective series of image-pixel signals line by line from said first section and said second section of said image-sensing area, a leading image-pixel signal of the image-pixel signals included in each line being farthest away from a boundary between said first section and said second section, a trailing image-pixel signal of the image-pixel signals included in each line being nearest to said boundary and a regulator correspondingly regulating respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, so that a gradual reduction occurs, resulting in both levels of the trailing image-pixel signals, derived from said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, which is cyclically varied from a minimum value to a maximum value, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first section and said second section on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 14

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area of a solid-type image sensor, which is constructed by combining at least two small-sized solid-type image sensors with each other such that said image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of said small-sized solid-type image sensors, respectively, said signal processor comprising: an image-pixel signal reader that simultaneously and correspondingly reads two respective series of image-pixel signals line by line from said first section and said second section of said image-sensing area, a leading image-pixel signal of the image-pixel signals included in each line being farthest away from a boundary between said first section and said second section, a trailing image-pixel signal of the image-pixel signals included in each line being nearest to said boundary and a regulator correspondingly regulating respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, so that a gradual reduction occurs, resulting in both levels of the trailing image-pixel signals, derived from said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, which is cyclically varied from a minimum value to a maximum value, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first section and said second section on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 15

An image-pixel signal processor as set forth in claim 10 , wherein said first level-changer and said second level-changer comprise a first voltage-controlled amplifier and a second voltage-controlled amplifier, and a magnification factor of each voltage-controlled amplifier is controlled in accordance with a variation of an inputted control voltage, the inputted control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor.

Claim 16

The image-pixel signal processor of claim 11 , wherein said first level detector outputs a voltage signal (V 1st ) as the detected level of the image-pixel signal derived from said first section, said second level detector outputs a voltage signal (V 2nd ) as the detected level of the image-pixel signal derived from said second section, and said calculator outputs a voltage signal (V 1st -V 2nd ) as the differential level between the levels of the voltage signals outputted from said first level-changer and said second level- changer, the respective control voltages (VC 1st and VC 2nd ) of said first voltage-controlled amplifier and said second voltage-controlled amplifier being defined as follows: VC 1st =(1−WF)V 1st +WF*V 2nd VC 2nd =(1−WF)V 2nd +WF*V 1st where WF represents the weight-factor (0≦WF≦1).

Claim 17

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area of a solid-type image sensor, which is constructed by combining at least two small-sized solid-type image sensors with each other such that said image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of said small-sized solid-type image sensors, respectively, a vertical boundary being defined between said first section and said second section, said signal processor comprising: an image-pixel signal reader reading respective series of image-pixel signals, from a leading line of said first section and said second section, by vertically transferring said plurality of image-pixel signals in a line by line succession, and by horizontally transferring a vertically-transferred leading line of said plurality of image-pixel signals, a leading image-pixel signal of the image-pixel signals included in each line being farthest from the vertical boundary between said first section and said second section, a trailing image-pixel signal of the image-pixel signals included in each line being nearest to said vertical boundary; and a regulator correspondingly regulating respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, so that a gradual reduction occurs, resulting in both levels of the trailing image-pixel signals, derived from said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, said weight-factor being cyclically varied from a minimum value to a maximum value in accordance with a series of clock pulses, on the basis of which the vertical transfer of the plurality of image-pixel signals is carried out in each of said first section and said second section, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first section and said second section on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 18

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area of a solid-type image sensor, which is constructed by combining at least two small-sized solid-type image sensors with each other such that said image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of said small-sized solid-type image sensors, respectively, a vertical boundary being defined between said first section and said second section, said signal processor comprising: an image-pixel signal reader reading respective series of image-pixel signals, from a leading line of said first section and said second section, by vertically transferring said plurality of image-pixel signals in a line by line succession, and by horizontally transferring a vertically-transferred leading line of said plurality of image-pixel signals, a leading image-pixel signal of the image-pixel signals included in each line being farthest from the vertical boundary between said first section and said second section, a trailing image-pixel signal of the image-pixel signals included in each line being nearest to said vertical boundary; and a regulator correspondingly regulating respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, so that a gradual reduction occurs, resulting in both levels of the trailing image-pixel signals, derived from said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, said weight-factor being cyclically varied from a minimum value to a maximum value in accordance with a series of clock pulses, on the basis of which the vertical transfer of the plurality of image-pixel signals is carried out in each of said first section and said second section, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first section and said second section on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 19

An image-pixel signal processor as set forth in claim 13 , wherein said first level-changer and said second level-changer comprise a first voltage-controlled amplifier and a second voltage-controlled amplifier, and a magnification factor of each voltage-controlled amplifier is controlled in accordance with a variation of an inputted control voltage, the inputted control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor.

Claim 20

The image-pixel signal processor of claim 14 , wherein said first level detector outputs a voltage signal (V 1st ) as the detected level of the image-pixel signal derived from said first section, said second level detector outputs a voltage signal (V 2nd ) as the detected level of the image-pixel signal derived from said second section, and said calculator outputs a voltage signal (V 1st -V 2nd ) as the differential level between the levels of the voltage signals outputted from said first level-changer and said second level-changer, respective control voltages (VC 1st and VC 2nd ) of said first voltage-controlled amplifier and said second voltage-controlled amplifier being defined as follows: VC 1st =(1−WF)V 1st +WF*V 2nd VC 2nd =(1−WF)V 2nd +WF*V 1st where WF represents the weight-factor (0≦WF≦1).

Claim 21

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area of a solid-type image sensor, which is constructed by combining at least two small-sized solid-type image sensors with each other such that said image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of said small-sized solid-type image sensors, respectively, a horizontal boundary being defined between said first section and said second section, said signal processor comprising: an image-pixel signal reader that reads respective series of image-pixel signals, from a leading line of said first and second sections, by vertically transferring said plurality of image-pixel signals in a line by line succession, and by horizontally transferring a vertically-transferred leading line of said plurality of image-pixel signals, a leading series of said plurality of image-pixel signals, first to be horizontally transferred from said first section and said second section, being farthest from the horizontal boundary between said first section and said second section, a trailing series of said plurality of image-pixel signals, last to be horizontally transferred from said first section and said second section, being nearest to said horizontal boundary; and a regulator correspondingly regulating respective differences between levels, represented by the image-pixel signals in respective lines, derived from said first section, and corresponding levels, represented by the image-pixel signals in respective lines, derived from said second section, so that a gradual reduction occurs, resulting in both levels, represented by the image-pixel signals in the trailing lines of said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, said weight-factor being cyclically varied from a minimum value to a maximum value in accordance with a series of clock pulses, on the basis of which the horizontal transfer of the plurality of image-pixel signals is carried out in each of said first section and said second section, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first section and said second section on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 22

An image-pixel signal processor that processes image-pixel signals obtained from an image-sensing area of a solid-type image sensor, which is constructed by combining at least two small-sized solid-type image sensors with each other such that said image-sensing area is formed of a first section and a second section corresponding to image-sensing areas of said small-sized solid-type image sensors, respectively, a horizontal boundary being defined between said first section and said second section, said signal processor comprising: an image-pixel signal reader that reads respective series of image-pixel signals, from a leading line of said first and second sections, by vertically transferring said plurality of image-pixel signals in a line by line succession, and by horizontally transferring a vertically-transferred leading line of said plurality of image-pixel signals, a leading series of said plurality of image-pixel signals, first to be horizontally transferred from said first section and said second section, being farthest from the horizontal boundary between said first section and said second section, a trailing series of said plurality of image-pixel signals, last to be horizontally transferred from said first section and said second section, being nearest to said horizontal boundary; and a regulator correspondingly regulating respective differences between levels, represented by the image-pixel signals in respective lines, derived from said first section, and corresponding levels, represented by the image-pixel signals in respective lines, derived from said second section, so that a gradual reduction occurs, resulting in both levels, represented by the image-pixel signals in the trailing lines of said first section and said second section, being substantially coincident with each other, wherein said regulator comprises: a first level-changer that changes a level of each image-pixel signal derived from said first section; a second level-changer that changes a level of each image-pixel signal derived from said second section; a first level-detector that detects a level of the image-pixel signal outputted from said first level-changer; a second level-detector that detects a level of the image-pixel signal outputted from said second level-changer; a calculator that calculates a differential level between the levels of the image-pixel signals outputted from said first level-changer and said second level-changer; and a weight-factor multiplier that multiplies the differential level by a weight-factor, said weight-factor being cyclically varied from a minimum value to a maximum value in accordance with a series of clock pulses, on the basis of which the horizontal transfer of the plurality of image-pixel signals is carried out in each of said first section and said second section, wherein said first level-changer and said second level-changer correspondingly change the levels of the image-pixel signals derived from said first section and said second section on the basis of the differential level multiplied by the cyclically-varied weight-factor, such that the regulation of said respective differences between levels of the image-pixel signals in each line, derived from said first section, and the corresponding image-pixel signals in each line, derived from said second section, is carried out.

Claim 23

An image-pixel signal processor as set forth in claim 15 , wherein said first level-changer and said second level-changer comprise a first voltage-controlled amplifier and a second voltage-controlled amplifier, and a magnification factor of each voltage-controlled amplifier is controlled in accordance with a variation of an inputted control voltage, the inputted control voltage being set on the basis of the differential level multiplied by the cyclically-varied weight-factor.

Claim 24

The image-pixel signal processor of claim 17 , wherein said first level detector outputs a voltage signal (V 1st ) as the detected level of the image-pixel signal derived from said first section, said second level detector outputs a voltage signal (V 2nd ) as the detected level of the image-pixel signal derived from said second section, and said calculator outputs a voltage signal (V 1st -V 2nd ) as the differential level between the levels of the voltage signals outputted from said first level-changer and said second level-changer, respective control voltages (VC 1st and VC 2nd ) of said first voltage-controlled amplifier and said second voltage-controlled amplifier being defined as follows: VC 1st =(1−WF)V 1st +WF*V 2nd VC 2nd =(1−WF)V 2nd +WF*V 1st where WF represents the weight-factor (0≦WF≦1).