US6336209B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Information processing system that processes portions of an application program using programmable logic circuits
Assignee: Fujifilm Business Innovation Corp
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Filing: 1999-03-29
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Granted: 2002-01-01
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Expires: 2019-03-29
Abstract
Abstract By reusing circuit information designed in the past, the amount of computation for combining circuit information for layout and wirings is significantly reduced. A memory part stores a plurality of pieces of circuit information for forming circuits in programmable logic circuits. Each of pieces of the circuit information has an identifier of its own circuit information, and in the case where part or all of the circuit information is formed with other circuit information, has the identifiers of the other circuit information as reference identifiers, as circuit data thereof. An acquisition part passes specification circuit information from an application program to an editing part, obtains circuit information of a specified circuit, sent from the editing part, and forms the specified circuit in the programmable logic circuits according to the circuit information. The editing part generates circuit information of a circuit specified by specification information from the acquisition part from circuit information of the specified circuit and other circuit information indicated by reference identifiers, obtained from the memory part.
Inventors
- 👤 Yoshio Nishihara
- 👤 Yoshihide Sato
- 👤 Norikazu Yamada
- 👤 Hiroyuki Miyake
- 👤 Eigo Nakagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:22
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; G06F15/00; G06F15/76; G06F15/78; G06F15/7867
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
169 words
An information processing system that performs at least part of processing of an application program with programmable logic circuits, comprising: a processing part that includes said programmable logic circuits and performs processing using circuits formed in said programmable logic circuits by instructions from said application program; a memory part that stores a plurality of pieces of circuit information for forming said circuits in said programmable logic circuits; an editing part that includes a function to generate circuit information of one circuit specified by specification information by using the plurality of pieces of circuit information stored in said memory part; and an acquisition part that, to identify a circuit to be formed in said programmable logic circuits, passes information specified by said application program, as said specification information, to said editing part, obtains circuit information of the circuit specified by said specification information wherein said circuit information arrives from said editing part, and forms said specified circuit in said programmable logic circuits of said processing part by said circuit information.
Claim 2
Dependent Claim
169 words
An information processing system that performs at least part of processing of an application program with programmable logic circuits, comprising: a processing part that includes said programmable logic circuits and performs processing using circuits formed in said programmable logic circuits by instructions from said application program; a memory part that stores a plurality of pieces of circuit information for forming said circuits in said programmable logic circuits; an editing part that includes a function to generate circuit information of one circuit specified by specification information by using the plurality of pieces of circuit information stored in said memory part; and an acquisition part that, to identify a circuit to be formed in said programmable logic circuits, passes information specified by said application program, as said specification information, to said editing part, obtains circuit information of the circuit specified by said specification information wherein said circuit information arrives from said editing part, and forms said specified circuit in said programmable logic circuits of said processing part by said circuit information.
Claim 3
Dependent Claim
38 words
The information processing system according to claim 1 , wherein a portion constituting said memory part, a portion constituting said editing part, and a portion constituting said acquisition part and said processing part are connected over a network.
Claim 4
Dependent Claim
115 words
The information processing system according to claim 1 , wherein each of a plurality of pieces of circuit information stored in said memory part has an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, has the identifiers of said other circuit information as reference identifiers, as circuit data for forming circuits in said programmable logic circuits; and said editing part generates circuit information of a circuit specified by said specification information passed from said acquisition part by obtaining the circuit information of said specified circuit and the other circuit information indicated by said reference identifiers from said memory part.
Claim 5
Dependent Claim
105 words
The information processing system according to claim 3 , wherein said editing part, in response to said specification information from said acquisition part, inquires of said memory part about circuit information of a circuit specified by said specification information by an identifier thereof; said memory part, in response to the inquiry from said editing part, if circuit information indicated by said identifier at the inquiry contains a reference identifier, returns the reference identifier to said editing part; and said editing part uses said reference identifier obtained from said memory part to obtain said other circuit information indicated by said reference identifier from said memory part.
Claim 6
Dependent Claim
219 words
The information processing system according to claim 1 , wherein each of said plurality of pieces of circuit information stored in said memory part comprises a circuit data unit and an additional information unit thereof; said additional information unit contains an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, contains the identifiers of said other circuit information as reference identifiers; said circuit data unit is for forming circuits in said programmable logic circuits, and in the case where part or all of said circuit information is formed with other circuit information, circuit data of the part or all of said circuit information is described using said reference identifiers; said editing part, in response to said specification information from said acquisition part, inquires of said memory part about circuit information of a circuit specified by said specification information by an identifier thereof; said memory part, in response to the inquiry from said editing part, if said additional information unit of circuit information indicated by said identifier at the inquiry contains a reference identifier, returns the reference identifier to said editing part; and said editing part uses said reference identifier obtained from said memory part to obtain said other circuit information from said memory part.
Claim 7
Dependent Claim
88 words
The information processing system according to claim 5 , wherein the circuit data unit of said circuit information stored in said memory part is described by pairs of the address of a configuration memory of said programmable logic circuits and circuit data stored in the address; and in the case where part or all of said circuit information is formed with other circuit information, said reference identifiers are described as circuit data of addresses corresponding to positions where said other circuit information is referenced in said circuit information.
Claim 8
Dependent Claim
82 words
The information processing system according to claim 6 , wherein said editing part links said other circuit information corresponding to said reference identifier to circuit information in which said reference identifier is contained, in such a way that the address at which said reference identifier is described as circuit data of circuit information of a circuit specified by said specification information is added to all the addresses of the circuit data unit of said other circuit information corresponding to said reference identifier.
Claim 9
Dependent Claim
82 words
The information processing system according to claim 6 , wherein the respective additional information units of a plurality of pieces of circuit information stored in said memory part contain pairs of a signal input port name and a signal output port name of circuits formed in said programmable logic circuits, and pairs of the coordinates of a signal input port and a signal output port indicated by said signal input port name and signal output port name on said programmable logic circuits.
Claim 10
Dependent Claim
86 words
The information processing system according to claim 8 , wherein said editing part links said other circuit information corresponding to said reference identifier to circuit information in which said reference identifier is contained, by adding an offset coordinate to the coordinates of signal input ports and signal output ports of circuit information corresponding to said reference identifier, the offset coordinate being calculated from the address where said reference identifier is described as the circuit data of circuit information of a circuit specified by said specification information.
Claim 11
Dependent Claim
164 words
The information processing system according to claim 8 , wherein said acquisition part separates circuit information obtained from said editing part into pairs of the addresses of configuration memories of said programmable logic circuits and circuit data and pairs of a signal input port name and a signal output port name of circuits formed in said programmable logic circuits and the coordinates of a signal input port and a signal output port indicated by said signal input port name and signal output port name; loads pairs of the address of a configuration memory of said programmable logic circuits and circuit data into said processing part to form circuits in said programmable logic circuits; and passes, to said application program, pairs of said signal input port name and signal output port name of circuits formed in said programmable logic circuits and the coordinates of a signal input port and a signal output port indicated by said signal input port name and signal output port name.
Claim 12
Dependent Claim
76 words
The information processing system according to claim 10 , wherein part of said application program is processed in said processing part by inputting and outputting data to and from said processing part based on pairs of the signal input port name and signal output port name of circuits formed in said programmable logic circuits and the coordinates of ports corresponding to said signal input port name and signal output port name, passed from said acquisition part.
Claim 13
Dependent Claim
132 words
A circuit information management method which stores in a memory part a plurality of pieces of circuit information of circuits formed in programmable logic circuits, with an identifier assigned to each of them, and when the identifier of a piece of said circuit information is specified, reads the corresponding part of said circuit information from said memory part to form said corresponding part in said programmable logic circuits, wherein each of said plurality of pieces of the circuit information stored in said memory part has an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, has the identifiers of said other circuit information as reference identifiers, as circuit data for forming circuits in said programmable logic circuits.
Claim 14
Dependent Claim
132 words
A circuit information management method which stores in a memory part a plurality of pieces of circuit information of circuits formed in programmable logic circuits, with an identifier assigned to each of them, and when the identifier of a piece of said circuit information is specified, reads the corresponding part of said circuit information from said memory part to form said corresponding part in said programmable logic circuits, wherein each of said plurality of pieces of the circuit information stored in said memory part has an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, has the identifiers of said other circuit information as reference identifiers, as circuit data for forming circuits in said programmable logic circuits.
Claim 15
Dependent Claim
185 words
A circuit information management method which stores in a memory part a plurality of pieces of circuit information of circuits formed in programmable logic circuits, with an identifier assigned to each of them, and when the identifier of a piece of said circuit information is specified, reads the corresponding part of said circuit information from said memory part to form said corresponding part in said programmable logic circuits, wherein each of said plurality of pieces of the circuit information stored in said memory part comprises a circuit data unit and an additional information unit thereof; said additional information unit contains an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, contains the identifiers of said other circuit information as reference identifiers; and said circuit data unit is for forming circuits in said programmable logic circuits, and in the case where part or all of said circuit information is formed with other circuit information, circuit data of the part or all of said circuit information is described using said reference identifiers.
Claim 16
Dependent Claim
185 words
A circuit information management method which stores in a memory part a plurality of pieces of circuit information of circuits formed in programmable logic circuits, with an identifier assigned to each of them, and when the identifier of a piece of said circuit information is specified, reads the corresponding part of said circuit information from said memory part to form said corresponding part in said programmable logic circuits, wherein each of said plurality of pieces of the circuit information stored in said memory part comprises a circuit data unit and an additional information unit thereof; said additional information unit contains an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, contains the identifiers of said other circuit information as reference identifiers; and said circuit data unit is for forming circuits in said programmable logic circuits, and in the case where part or all of said circuit information is formed with other circuit information, circuit data of the part or all of said circuit information is described using said reference identifiers.
Claim 17
Dependent Claim
89 words
The circuit information management method according to claim 13 , wherein the circuit data unit of said circuit information stored in said memory part is described by pairs of the address of a configuration memory of said programmable logic circuits and circuit data stored in the address; and in the case where part or all of said circuit information is formed with other circuit information, said reference identifiers are described as circuit data of addresses corresponding to positions where said other circuit information is referenced in said circuit information.
Claim 18
Dependent Claim
84 words
The circuit information management method according to claim 13 , wherein the additional information unit of each of said plurality of pieces of circuit information stored in said memory part is described with pairs of a signal input port name and a signal output port name of circuits formed in said programmable logic circuits and the coordinates of a signal input port and a signal output port indicated by the signal input port name and signal output port name on said programmable logic circuits.
Claim 19
Dependent Claim
90 words
A circuit information storage device in which a plurality of pieces of circuit information of circuits formed in programmable logic circuits is stored with an identifier assigned to each of them, wherein each of said plurality of pieces of the circuit information has an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, has the identifiers of said other circuit information as reference identifiers, as circuit data for forming circuits in said programmable logic circuits.
Claim 20
Dependent Claim
90 words
A circuit information storage device in which a plurality of pieces of circuit information of circuits formed in programmable logic circuits is stored with an identifier assigned to each of them, wherein each of said plurality of pieces of the circuit information has an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, has the identifiers of said other circuit information as reference identifiers, as circuit data for forming circuits in said programmable logic circuits.
Claim 21
Dependent Claim
143 words
A circuit information storage device in which a plurality of pieces of circuit information of circuits formed in programmable logic circuits is stored with an identifier assigned to each of them, wherein each of said plurality of pieces of the circuit information comprises a circuit data unit and an additional information unit thereof; said additional information unit contains an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, contains the identifiers of said other circuit information as reference identifiers; and said circuit data unit is for forming circuits in said programmable logic circuits, and in the case where part or all of said circuit information is formed with other circuit information, circuit data of the part or all of said circuit information is described using said reference identifiers.
Claim 22
Dependent Claim
143 words
A circuit information storage device in which a plurality of pieces of circuit information of circuits formed in programmable logic circuits is stored with an identifier assigned to each of them, wherein each of said plurality of pieces of the circuit information comprises a circuit data unit and an additional information unit thereof; said additional information unit contains an identifier of its own circuit information, and in the case where part or all of said circuit information is formed with other circuit information, contains the identifiers of said other circuit information as reference identifiers; and said circuit data unit is for forming circuits in said programmable logic circuits, and in the case where part or all of said circuit information is formed with other circuit information, circuit data of the part or all of said circuit information is described using said reference identifiers.
Claim 23
Dependent Claim
84 words
The circuit information storage device according to claim 17 , wherein the circuit data unit of said circuit information is described by pairs of the address of a configuration memory of said programmable logic circuits and circuit data stored in the address; and in the case where part or all of said circuit information is formed with other circuit information, said reference identifiers are described as circuit data of addresses corresponding to positions where said other circuit information is referenced in said circuit information.
Claim 24
Dependent Claim
84 words
The circuit information storage device according to claim 17 , wherein the additional information unit of each of said plurality of pieces of circuit information stored in said memory part is described with pairs of a signal input port name and a signal output port name of circuits formed in said programmable logic circuits and the coordinates of a signal input port and a signal output port indicated by said signal input port name and signal output port name on said programmable logic circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-31 | 2005-07-02 | 2006-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-31 | 2009-07-02 | 2010-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-31 | 2013-07-02 | 2014-01-01 | $7700.00 | Window Closed / Lapsed |