Tap with scannable control circuit for selecting first test data register in tap or second test data register in tap linking module for scanning data

Claim 2

A scan test architecture, comprising: a scan controller; a first scannable test data register coupled to said scan controller for scanning data in a test interface in response to a first scan control signal generated by said scan controller; a second scannable test data register coupled to a second scan control signal for scanning data in a test access port linking module separate from the test interface in response to said second scan control signal, said second scan control signal generated independently of said scan controller; and a scannable control circuit included in the test interface having an output for selecting said first scannable register for scanning and also for alternatively selecting said second scannable register for scanning.

Claim 5

An integrated circuit, comprising: a test bus; a target circuit; a test interface coupled between said test bus and said target circuit, said test interface including a scan controller and a first scannable test data register coupled to said scan controller for scanning data in response to a first scan control signal generated by said scan controller, and said test interface including a scannable control circuit responsive to a first control code scanned thereinto for selecting said first test data register to be scanned and for providing a control signal to said target circuit; and a second scannable test data register coupled to a second scan control signal for scanning data in a test access port linking module separate from the test interface in response to said second scan control signal, said second scan control signal generated independently of said scan controller, said scannable control circuit responsive to a second control code scanned thereinto for selecting said second test data register to be scanned and for providing said control signal to said target circuit.

Claim 6

An integrated circuit, comprising: a test bus; a target circuit; a test interface coupled between said test bus and said target circuit, said test interface including a scan controller and a first scannable test data register coupled to said scan controller for scanning data in response to a first scan control signal generated by said scan controller, and said test interface including a scannable control circuit responsive to a first control code scanned thereinto for selecting said first test data register to be scanned and for providing a control signal to said target circuit; and a second scannable test data register coupled to a second scan control signal for scanning data in a test access port linking module separate from the test interface in response to said second scan control signal, said second scan control signal generated independently of said scan controller, said scannable control circuit responsive to a second control code scanned thereinto for selecting said second test data register to be scanned and for providing said control signal to said target circuit.