US6322934B1
Expired / Lapsed
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Method for making integrated circuits including features with a relatively small critical dimension
Assignee: Nokia of America Corp
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Filing: 1999-09-30
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Granted: 2001-11-27
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Expires: 2019-09-30
Abstract
Abstract A method is for making an integrated circuit on a semiconductor wafer, where the integrated circuit includes circuit features having a desired, relatively small, critical dimension. The method preferably comprises the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension. The designing step preferably includes determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift. The method preferably includes steps of fabricating the reticle and using the reticle to make the integrated circuit on the semiconductor wafer based on the plurality of exposure steps. The present invention recognizes that the scaling factor is not a single number, but instead is a non-linear function which is also based upon the shift between exposure steps.
Inventors
- 👤 John David Cuthbert
- 👤 Feng Jin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:47
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70466; H; H10; H10D; H10D99/00; G03F7/20; G03F7/2022
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
143 words
A method for making an integrated circuit on a semiconductor wafer, the integrated circuit including circuit features having a desired, relatively small, critical dimension, the method comprising the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension; the designing step including determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift; and fabricating the reticle and using the reticle to make the integrated circuit on the semiconductor wafer based on the plurality of exposure steps.
Claim 2
Independent Claim
143 words
A method for making an integrated circuit on a semiconductor wafer, the integrated circuit including circuit features having a desired, relatively small, critical dimension, the method comprising the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension; the designing step including determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift; and fabricating the reticle and using the reticle to make the integrated circuit on the semiconductor wafer based on the plurality of exposure steps.
Claim 3
Dependent Claim
14 words
A method according to claim 1 wherein the step of determining comprises empirically determining.
Claim 4
Dependent Claim
15 words
A method according to claim 1 wherein the scaling factor function is a non-linear function.
Claim 5
Dependent Claim
22 words
A method according to claim 1 wherein the scaling factor function is also a function of a photolithography tool using the reticle.
Claim 6
Dependent Claim
22 words
A method according to claim 1 wherein the scaling factor function is also a function of a photoresist on the semiconductor wafer.
Claim 7
Dependent Claim
32 words
A method according to claim 1 wherein the step of using the reticle comprises applying a photoresist layer on the semiconductor wafer and using the reticle to selectively expose the photoresist layer.
Claim 8
Dependent Claim
20 words
A method according to claim 6 further comprising the step of removing portions of the photoresist layer after the exposing.
Claim 9
Dependent Claim
23 words
A method according to claim 1 wherein the integrated circuit includes circuit features for gates of at least some relatively fast MOS transistors.
Claim 10
Dependent Claim
34 words
A method according to claim 1 wherein the integrated circuit includes circuit features for fast MOS transistors and slow MOS transistors; and wherein the reticle is used for both fast and slow MOS transistors.
Claim 11
Dependent Claim
31 words
A method according to claim 1 wherein the integrated circuit includes circuit features that are generally rectangular in shape; and wherein the shift between exposing steps is in a diagonal direction.
Claim 12
Dependent Claim
15 words
A method according to claim 1 wherein the reticle is devoid of phase shifting portions.
Claim 13
Independent Claim
145 words
A method for defining circuit features having a desired, relatively small, critical dimension on a semiconductor wafer, the method comprising the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension; the designing step including empirically determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift; fabricating the reticle; coating the semiconductor wafer with a photoresist layer; and using the reticle for the plurality of exposure steps of the photoresist layer with the shift between adjacent exposure steps.
Claim 14
Independent Claim
145 words
A method for defining circuit features having a desired, relatively small, critical dimension on a semiconductor wafer, the method comprising the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension; the designing step including empirically determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift; fabricating the reticle; coating the semiconductor wafer with a photoresist layer; and using the reticle for the plurality of exposure steps of the photoresist layer with the shift between adjacent exposure steps.
Claim 15
Dependent Claim
15 words
A method according to claim 12 wherein the scaling factor function is a non-linear function.
Claim 16
Dependent Claim
22 words
A method according to claim 12 wherein the scaling factor function is also a function of a photolithography tool using the reticle.
Claim 17
Dependent Claim
23 words
A method according to claim 12 wherein the scaling factor function is also a function of the photoresist layer on the semiconductor wafer.
Claim 18
Dependent Claim
21 words
A method according to claim 12 further comprising the step of removing portions of the photoresist layer after the exposing steps.
Claim 19
Dependent Claim
23 words
A method according to claim 12 wherein the integrated circuit includes circuit features for gates of at least some relatively fast MOS transistors.
Claim 20
Dependent Claim
34 words
A method according to claim 12 wherein the integrated circuit includes circuit features for fast MOS transistors and slow MOS transistors; and wherein the reticle is used for both fast and slow MOS transistors.
Claim 21
Dependent Claim
31 words
A method according to claim 12 wherein the integrated circuit includes circuit features that are generally rectangular in shape; and wherein the shift between exposing steps is in a diagonal direction.
Claim 22
Dependent Claim
15 words
A method according to claim 12 wherein the reticle is devoid of phase shifting portions.
Claim 23
Independent Claim
101 words
A method for designing a reticle including pattern features having a critical dimension to form corresponding circuit features in an integrated circuit on a semiconductor wafer based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have desired, relatively small, critical dimension, the method comprising the step of: determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift.
Claim 24
Independent Claim
101 words
A method for designing a reticle including pattern features having a critical dimension to form corresponding circuit features in an integrated circuit on a semiconductor wafer based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have desired, relatively small, critical dimension, the method comprising the step of: determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift.
Claim 25
Dependent Claim
14 words
A method according to claim 21 wherein the step of determining comprises empirically determining.
Claim 26
Dependent Claim
15 words
A method according to claim 21 wherein the scaling factor function is a non-linear function.
Claim 27
Dependent Claim
22 words
A method according to claim 21 wherein the scaling factor function is also a function of a photolithography tool using the reticle.
Claim 28
Dependent Claim
22 words
A method according to claim 21 wherein the scaling factor function is also a function of a photoresist on the semiconductor wafer.
Claim 29
Dependent Claim
23 words
A method according to claim 21 wherein the integrated circuit includes circuit features for gates of at least some relatively fast MOS transistors.
Claim 30
Dependent Claim
34 words
A method according to claim 21 wherein the integrated circuit includes circuit features for fast MOS transistors and slow MOS transistors; and wherein the reticle is used for both fast and slow MOS transistors.
Claim 31
Dependent Claim
31 words
A method according to claim 21 wherein the integrated circuit includes circuit features that are generally rectangular in shape; and wherein the shift between exposing steps is in a diagonal direction.
Claim 32
Dependent Claim
15 words
A method according to claim 21 wherein the reticle is devoid of phase shifting portions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-26 | 2005-05-28 | 2005-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-26 | 2009-05-28 | 2009-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-26 | 2013-05-28 | 2013-11-27 | $7700.00 | Window Closed / Lapsed |