US6320364B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current source circuit
Assignee: Toyota Industries Corp
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Filing: 2000-09-27
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Granted: 2001-11-20
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Expires: 2020-09-27
Abstract
Abstract A start signal is supplied to MOS transistor Q 8, MOS transistor Q 8 is turned on, the first current mirror circuit is driven, and the same mirror current flows in MOS transistors Q 4 -Q 7. Then, of two MOS transistors Q 8 and Q 9 that compose the second current mirror circuit, to MOS transistor Q 8 is connected a resistor R 2 and to MOS transistor Q 9 is supplied a reference signal (Vref). According to such a configuration, reference current (Iref) that is generated in resistor R 2 becomes current corresponding to the reference signal (Vref), and thereby output current (Iout) is outputted from MOS transistor Q 7 based on this reference current (Iref).
Inventors
- 👤 Tetsuo Tateishi
- 👤 Katsutomi Harada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:07
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
135 words
A current source circuit for minimizing the time lag between a reference signal and an output current, the current source circuit comprising: a first current mirror circuit for outputting the output current; a second current mirror circuit connected to the first current mirror circuit, and the second current mirror circuit connected to a resistor for generating a reference current corresponding to the output current; a reference signal supply circuit for supplying the reference signal to the second current mirror circuit, wherein the reference signal supplies current for generating the reference current; and an input terminal connected to at least one of the first current mirror circuit and the second current mirror circuit and the input terminal receives a start signal that drives one of the first current mirror circuit and the second current mirror circuit.
Claim 2
Dependent Claim
135 words
A current source circuit for minimizing the time lag between a reference signal and an output current, the current source circuit comprising: a first current mirror circuit for outputting the output current; a second current mirror circuit connected to the first current mirror circuit, and the second current mirror circuit connected to a resistor for generating a reference current corresponding to the output current; a reference signal supply circuit for supplying the reference signal to the second current mirror circuit, wherein the reference signal supplies current for generating the reference current; and an input terminal connected to at least one of the first current mirror circuit and the second current mirror circuit and the input terminal receives a start signal that drives one of the first current mirror circuit and the second current mirror circuit.
Claim 3
Dependent Claim
29 words
The current source circuit of claim 1 further comprising: a third current mirror circuit that prevents current from flowing from the second current mirror circuit to the reference signal.
Claim 4
Dependent Claim
16 words
The current source circuit of claim 2 , wherein the reference signal is a predetermined waveform.
Claim 5
Dependent Claim
15 words
The current source circuit of claim 3 wherein the predetermined waveform is a triangular wave.
Claim 6
Dependent Claim
15 words
The current source circuit of claim 4 wherein the predetermined waveform is a sine wave.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-19 | 2005-05-21 | 2005-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-19 | 2009-05-21 | 2009-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-19 | 2013-05-21 | 2013-11-20 | $7700.00 | Window Closed / Lapsed |