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US6319798B1
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Method for reducing lateral dopant gradient in source/drain extension of MOSFET
Assignee: GlobalFoundries Inc
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Filing: 1999-09-23
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Granted: 2001-11-20
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Expires: 2019-09-23
Abstract
Abstract A method for reducing lateral dopant gradient diffusion in the source/drain extension (SDE) region of a MOSFET includes forming the deep source and drain using high temperature dopant activation annealing, and then implanting a preamorphization species in an amorphized extension region that is to become the SDE region. Then, both SDE dopant and, if desired, halo dopant are implanted into the amorphized extension region and activated using relatively low temperature annealing, thereby reducing the thermal budget of the process and concomitantly reducing unwanted dopant thermal diffusion.
Inventors
- 👤 Bin Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:03
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/015; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/208; H10P30/222; H10P30/225
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
90 words
A method for establishing at least one transistor on a semiconductor device, comprising: providing a semiconductor substrate; implanting source and drain dopants into the substrate to establish a source region and a drain region; heating the substrate to activate the dopants; then implanting at least one neutral ion species in the substrate between the source and drain regions to define an amorphous extension region; implanting at least a source/drain extension (SDE) dopant in the amorphous extension region; and heating at least the amorphous extension region to activate the SDE dopant.
Claim 2
Independent Claim
90 words
A method for establishing at least one transistor on a semiconductor device, comprising: providing a semiconductor substrate; implanting source and drain dopants into the substrate to establish a source region and a drain region; heating the substrate to activate the dopants; then implanting at least one neutral ion species in the substrate between the source and drain regions to define an amorphous extension region; implanting at least a source/drain extension (SDE) dopant in the amorphous extension region; and heating at least the amorphous extension region to activate the SDE dopant.
Claim 3
Dependent Claim
46 words
The method of claim 1 , wherein the substrate is heated to more than nine hundred fifty degrees Celsius (950° C.) to activate the source and drain dopants, and the amorphous extension region is heated to no more than nine hundred fifty degrees Celsius (950° C.).
Claim 4
Dependent Claim
36 words
The method of claim 2 , wherein the amorphous extension region is heated to no more than six hundred fifty degrees Celsius (650° C.) such that the SDE dopant is substantially not thermally diffused after activation.
Claim 5
Dependent Claim
41 words
The method of claim 1 , wherein the substrate defines a surface, and the neutral ion species is implanted in the substrate by directing a beam of the neutral ion species onto the surface at an oblique angle to the surface.
Claim 6
Dependent Claim
17 words
The method of claim 1 , further comprising implanting a halo dopant in the amorphous extension region.
Claim 7
Dependent Claim
55 words
The method of claim 5 , wherein the amorphous extension region defines a depth relative to a surface of the substrate, and the halo dopant is implanted to a halo depth of about one-half the depth of the amorphous extension region, the SDE dopant being implanted to a depth of about one-half the halo depth.
Claim 8
Dependent Claim
21 words
The method of claim 1 , wherein the neutral ion species includes at least one of: Silicon (Si) and Germanium (Ge).
Claim 9
Independent Claim
51 words
A method for making an ultra-large scale integration (ULSI) semiconductor device, comprising: establishing source and drain regions in a semiconductor substrate using a first activation temperature; then establishing a doped source/drain extension (SDE) region between the source and drain regions using a second activation temperature less than the first activation temperature.
Claim 10
Independent Claim
51 words
A method for making an ultra-large scale integration (ULSI) semiconductor device, comprising: establishing source and drain regions in a semiconductor substrate using a first activation temperature; then establishing a doped source/drain extension (SDE) region between the source and drain regions using a second activation temperature less than the first activation temperature.
Claim 11
Dependent Claim
22 words
The method of claim 8 , wherein the second activation temperature does not exceed nine hu ndred fifty degrees Celsius (950° C.).
Claim 12
Dependent Claim
21 words
The method of claim 9 , wherein the second activation temperature does not exceed six hundred fifty degrees Celsius (650° C.).
Claim 13
Dependent Claim
61 words
The method of claim 8 , further comprising: after activating the source and drain regions, implanting at least one neutral ion species in the substrate between the source and drain regions to define an amorphous extension region; implanting at least an SDE dopant in the amorphous extension region; then heating at least the amorphous extension region to the second activation temperature.
Claim 14
Dependent Claim
21 words
The method of claim 11 , wherein the neutral ion species includes at least one of: Silicon (Si) and Germanium (Ge).
Claim 15
Dependent Claim
41 words
The method of claim 11 , wherein the substrate defines a surface, and the neutral ion species is implanted in the substrate by directing a beam of the neutral ion species onto the surface at an oblique angle to the surface.
Claim 16
Dependent Claim
17 words
The method of claim 13 , further comprising implanting a halo dopant in the amorphous extension region.
Claim 17
Dependent Claim
55 words
The method of claim 14 , wherein the amorphous extension region defines a depth relative to a surface of the substrate, and the halo dopant is implanted to a halo depth of about one-half the depth of the amorphous extension region, the SDE dopant being implanted to a depth of about one-half the halo depth.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-19 | 2005-05-21 | 2005-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-19 | 2009-05-21 | 2009-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-19 | 2013-05-21 | 2013-11-20 | $7700.00 | Window Closed / Lapsed |