US6317860B1
Expired / Lapsed
US
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Electronic design automation tool for display of design profile
Assignee: Altera Corp
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Filing: 1997-10-27
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Granted: 2001-11-13
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Expires: 2017-10-27
Abstract
Abstract A technique accurately calculates utilization information for an electronic design to help optimize the design. After synthesis of the complete design, information including number of combinatorial logic cells, maximum number of levels of combinatorial logic cells, number of registered logic cells, and number of latch logic cells for each line of source code is displayed. The information is in a source file text editor or in a graphic editor. The technique maps back from logic cells to technology-independent gates and back to lines of source code taking into account synthesized logic cells, and displays how many logic cells a line of source code is responsible for producing. For post-synthesis netlists having no synthesized logic cells, gates are grouped according to which logic cell they correspond. For netlists with synthesized logic cells, regions of logic cells within the netlist are first identified. Starting from a non-synthesized logic cell, its inputs are traversed upstream to form a region of logic cells until either an input pin is reached or another non-synthesized logic cell is reached. Regions may overlap. Synthesized logic cells within more than one region contribute a fraction to each region. Next, regions of gates are identified in the gate-level netlist that correspond to each region of logic cells. Logic cells of each region are distributed among gates of the corresponding region. Logic cells are counted for a line of source code by identifying to which gates the line corresponds and summing the logic cells for those gates.
Inventors
- 👤 Francis B. Heile
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:37
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/60; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G01R31/3181; G01R31/3185; G01R31/318516; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0748; G06F11/22; G06F11/2294; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G06F30/34; G06F30/347; G06F8/65; G06F8/70; G06F8/71; G06Q; G06Q10/00; G06Q10/06; G06Q10/10; G06F2111/00; G06F2111/02; Y; Y10; Y10S; Y10S707/00; Y10S707/99951; Y10S707/99952; Y10S707/99953; Y10S707/99954
Claims Analysis
Total Claims: 52
Claim 1
Independent Claim
129 words
A computer-implemented method of providing utilization information to a designer of an electronic design for a PLD, said method comprising: generating a post-extraction netlist for said electronic design that includes a plurality of technology-independent gates; synthesizing said post-extraction netlist to produce a post-synthesis netlist of logic cells, said netlist of logic cells including a plurality of synthesized logic cells; marking said synthesized logic cells as being synthesized; distributing said netlist of logic cells among said post-extraction netlist of technology-independent gates, said synthesized logic cells being thereby distributed among said technology-independent gates; and providing utilization information to said designer based upon said distribution of said netlist of logic cells among said post-extraction netlist of technology-independent gates, said utilization information corresponding to a line of source code of said electronic design.
Claim 2
Dependent Claim
129 words
A computer-implemented method of providing utilization information to a designer of an electronic design for a PLD, said method comprising: generating a post-extraction netlist for said electronic design that includes a plurality of technology-independent gates; synthesizing said post-extraction netlist to produce a post-synthesis netlist of logic cells, said netlist of logic cells including a plurality of synthesized logic cells; marking said synthesized logic cells as being synthesized; distributing said netlist of logic cells among said post-extraction netlist of technology-independent gates, said synthesized logic cells being thereby distributed among said technology-independent gates; and providing utilization information to said designer based upon said distribution of said netlist of logic cells among said post-extraction netlist of technology-independent gates, said utilization information corresponding to a line of source code of said electronic design.
Claim 3
Dependent Claim
31 words
A method as recited in claim 1 wherein each of said synthesized logic cells has an output that does not correspond to any of said technology-independent gates of said post-extraction netlist.
Claim 4
Dependent Claim
48 words
A method as recited in claim 1 further comprising: grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell, whereby synthesized logic cells are taken into account during said distributing step.
Claim 5
Dependent Claim
60 words
A method as recited in claim 1 wherein said step of distributing said netlist of logic cells includes the sub-step of: distributing said netlist of logic cells among said post-extraction netlist of technology-independent gates such that the sum of all logic cells associated with said technology-independent gates is equal to the number of logic cells utilized in said electronic design.
Claim 6
Dependent Claim
43 words
A method as recited in claim 1 wherein said step of providing utilization information to said designer includes the sub-step of: providing information including the number of combinatorial logic cells, the number of registered logic cells and the number of latch logic cells.
Claim 7
Dependent Claim
87 words
A method as recited in claim 1 further comprising: calculating the maximum path length through a subset of said logic cells corresponding to a subset of said technology-independent gates, said subset of said technology-independent gates corresponding to a line of source code of said electronic design; and providing to said designer a timing delay for said line of source code based upon said calculated maximum path length, whereby said synthesized logic cells are taken into account in determining said timing delay for said line of source code.
Claim 8
Dependent Claim
149 words
A computer-implemented method of determining the number of logic cells associated with a line of source code of an electronic design for a PLD, said method comprising: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells; creating a plurality of synthesized logic cells during said compiling, said synthesized logic cells included in said plurality of logic cells; distributing said plurality of logic cells among said plurality of gates, said synthesized logic cells being thereby distributed among said plurality of gates; and determining a subset of said plurality of gates that correspond to said line of source code; and summing the number of logic cells distributed to said subset of said plurality of gates, thereby determining the number of logic cells associated with said line of source code.
Claim 9
Dependent Claim
149 words
A computer-implemented method of determining the number of logic cells associated with a line of source code of an electronic design for a PLD, said method comprising: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells; creating a plurality of synthesized logic cells during said compiling, said synthesized logic cells included in said plurality of logic cells; distributing said plurality of logic cells among said plurality of gates, said synthesized logic cells being thereby distributed among said plurality of gates; and determining a subset of said plurality of gates that correspond to said line of source code; and summing the number of logic cells distributed to said subset of said plurality of gates, thereby determining the number of logic cells associated with said line of source code.
Claim 10
Dependent Claim
30 words
A method as recited in claim 7 wherein each of said synthesized logic cells has an output that does not correspond to any of said gates of said gate-level netlist.
Claim 11
Dependent Claim
48 words
A method as recited in claim 7 further comprising: grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell, whereby synthesized logic cells are taken into account during said distributing step.
Claim 12
Dependent Claim
57 words
A method as recited in claim 7 wherein said step of distributing said plurality of logic cells includes the sub-step of: distributing said plurality of logic cells among said plurality of gates such that the sum of all logic cells associated with said gates is equal to the number of logic cells utilized in said electronic design.
Claim 13
Dependent Claim
63 words
A method as recited in claim 7 wherein said step of summing the number of logic cells includes the sub-steps of: summing the number of combinatorial logic cells; summing the number of registered logic cells; and summing the number of latch logic cells, whereby the number of combinatorial, registered and latch logic cells associated with said line of source code may be determined.
Claim 14
Dependent Claim
89 words
A method as recited in claim 7 further comprising: calculating the maximum path length through a subset of said logic cells corresponding to said subset of said plurality of gates, said subset of said plurality of gates corresponding to said line of source code of said electronic design; and providing to said designer a timing delay for said line of source code based upon said calculated maximum path length, whereby said synthesized logic cells are taken into account in determining said timing delay for said line of source code.
Claim 15
Dependent Claim
193 words
A computer-implemented method of providing the number of logic cells associated with a line of source code of an electronic design for a PLD, said method comprising: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells, said plurality of logic cells including a plurality of synthesized logic cells and a plurality of hard logic cells created during said compiling; grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell; determining a number of logic cells contributing to each of said regions taking into account overlapping regions; distributing said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates; and providing a final number of logic cells associated with said line of source code to said designer based upon said distribution of said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates.
Claim 16
Dependent Claim
193 words
A computer-implemented method of providing the number of logic cells associated with a line of source code of an electronic design for a PLD, said method comprising: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells, said plurality of logic cells including a plurality of synthesized logic cells and a plurality of hard logic cells created during said compiling; grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell; determining a number of logic cells contributing to each of said regions taking into account overlapping regions; distributing said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates; and providing a final number of logic cells associated with said line of source code to said designer based upon said distribution of said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates.
Claim 17
Dependent Claim
50 words
A method as recited in claim 13 wherein each of said synthesized logic cells has an output that does not correspond to any of said gates of said gate-level netlist, and each of said hard logic cells has an output that does correspond to a gate of said gate-level netlist.
Claim 18
Dependent Claim
85 words
A method as recited in claim 13 wherein said step of grouping said logic cells into regions includes the sub-step of: identifying a first hard logic cell in said post-synthesis netlist as belonging to a first region; and traversing the inputs to said first hard logic cell and including synthesized logic cells in said first region until either a hard logic cell is reached or an input pin is reached, whereby a first region of logic cells is identified that is one of said regions.
Claim 19
Dependent Claim
71 words
A method as recited in claim 13 wherein said step of distributing said number of logic cells includes the sub-step of: distributing said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates such that the sum of all logic cells associated with said plurality of gates is equal to the number of logic cells utilized in said electronic design.
Claim 20
Dependent Claim
64 words
A method as recited in claim 13 wherein said step of providing a final number of logic cells includes the sub-steps of: summing the number of combinatorial logic cells; summing the number of registered logic cells; and summing the number of latch logic cells, whereby the number of combinatorial, registered and latch logic cells associated with said line of source code may be determined.
Claim 21
Dependent Claim
89 words
A method as recited in claim 13 further comprising: calculating the maximum path length through a subset of said logic cells corresponding to a subset of said plurality of gates, said subset of said plurality of gates corresponding to said line of source code of said electronic design; and providing to said designer a timing delay for said line of source code based upon said calculated maximum path length, whereby said synthesized logic cells are taken into account in determining said timing delay for said line of source code.
Claim 22
Dependent Claim
159 words
A computer-implemented method of determining a timing delay associated with a line of source code of an electronic design for a PLD, said method comprising: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells; creating a plurality of synthesized logic cells during said compiling, said synthesized logic cells included in said plurality of logic cells; distributing said plurality of logic cells among said plurality of gates, said synthesized logic cells being thereby distributed among said plurality of gates; and determining a subset of said logic cells that correspond to said line of source code; and determining the maximum signal path length through said subset of said logic cells to provide a representation of said timing delay, whereby said synthesized logic cells are taken into account in determining said timing delay associated with said line of source code.
Claim 23
Dependent Claim
159 words
A computer-implemented method of determining a timing delay associated with a line of source code of an electronic design for a PLD, said method comprising: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells; creating a plurality of synthesized logic cells during said compiling, said synthesized logic cells included in said plurality of logic cells; distributing said plurality of logic cells among said plurality of gates, said synthesized logic cells being thereby distributed among said plurality of gates; and determining a subset of said logic cells that correspond to said line of source code; and determining the maximum signal path length through said subset of said logic cells to provide a representation of said timing delay, whereby said synthesized logic cells are taken into account in determining said timing delay associated with said line of source code.
Claim 24
Dependent Claim
30 words
A method as recited in claim 19 wherein each of said synthesized logic cells has an output that does not correspond to any of said gates of said gate-level netlist.
Claim 25
Dependent Claim
48 words
A method as recited in claim 19 further comprising: grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell, whereby synthesized logic cells are taken into account during said distributing step.
Claim 26
Dependent Claim
57 words
A method as recited in claim 19 wherein said step of distributing said plurality of logic cells includes the sub-step of: distributing said plurality of logic cells among said plurality of gates such that the sum of all logic cells associated with said gates is equal to the number of logic cells utilized in said electronic design.
Claim 27
Dependent Claim
139 words
A computer-readable medium comprising computer code for providing utilization information to a designer of an electronic design for a PLD, said computer code of said computer-readable medium effecting the following: generating a post-extraction netlist for said electronic design that includes a plurality of technology-independent gates; synthesizing said post-extraction netlist to produce a post-synthesis netlist of logic cells, said netlist of logic cells including a plurality of synthesized logic cells; marking said synthesized logic cells as being synthesized; distributing said netlist of logic cells among said post-extraction netlist of technology-independent gates, said synthesized logic cells being thereby distributed among said technology-independent gates; and providing utilization information to said designer based upon said distribution of said netlist of logic cells among said post-extraction netlist of technology-independent gates, said utilization information corresponding to a line of source code of said electronic design.
Claim 28
Dependent Claim
139 words
A computer-readable medium comprising computer code for providing utilization information to a designer of an electronic design for a PLD, said computer code of said computer-readable medium effecting the following: generating a post-extraction netlist for said electronic design that includes a plurality of technology-independent gates; synthesizing said post-extraction netlist to produce a post-synthesis netlist of logic cells, said netlist of logic cells including a plurality of synthesized logic cells; marking said synthesized logic cells as being synthesized; distributing said netlist of logic cells among said post-extraction netlist of technology-independent gates, said synthesized logic cells being thereby distributed among said technology-independent gates; and providing utilization information to said designer based upon said distribution of said netlist of logic cells among said post-extraction netlist of technology-independent gates, said utilization information corresponding to a line of source code of said electronic design.
Claim 29
Dependent Claim
32 words
A computer-readable medium as recited in claim 23 wherein each of said synthesized logic cells has an output that does not correspond to any of said technology-independent gates of said post-extraction netlist.
Claim 30
Dependent Claim
52 words
A computer-readable medium as recited in claim 23 further comprising computer code for: grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell, whereby synthesized logic cells are taken into account during said distributing step.
Claim 31
Dependent Claim
62 words
A computer-readable medium as recited in claim 23 wherein said computer code for distributing said netlist of logic cells includes computer code for: distributing said netlist of logic cells among said post-extraction netlist of technology-independent gates such that the sum of all logic cells associated with said technology-independent gates is equal to the number of logic cells utilized in said electronic design.
Claim 32
Dependent Claim
45 words
A computer-readable medium as recited in claim 23 wherein said computer code for providing utilization information to said designer includes computer code for: providing information including the number of combinatorial logic cells, the number of registered logic cells and the number of latch logic cells.
Claim 33
Dependent Claim
91 words
A computer-readable medium as recited in claim 23 further comprising computer code for: calculating the maximum path length through a subset of said logic cells corresponding to a subset of said technology-independent gates, said subset of said technology-independent gates corresponding to a line of source code of said electronic design; and providing to said designer a timing delay for said line of source code based upon said calculated maximum path length, whereby said synthesized logic cells are taken into account in determining said timing delay for said line of source code.
Claim 34
Dependent Claim
159 words
A computer-readable medium comprising computer code for determining the number of logic cells associated with a line of source code of an electronic design for a PLD, said computer code of said computer-readable medium effecting the following: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells; creating a plurality of synthesized logic cells during said compiling, said synthesized logic cells included in said plurality of logic cells; distributing said plurality of logic cells among said plurality of gates, said synthesized logic cells being thereby distributed among said plurality of gates; and determining a subset of said plurality of gates that correspond to said line of source code; and summing the number of logic cells distributed to said subset of said plurality of gates, thereby determining the number of logic cells associated with said line of source code.
Claim 35
Dependent Claim
159 words
A computer-readable medium comprising computer code for determining the number of logic cells associated with a line of source code of an electronic design for a PLD, said computer code of said computer-readable medium effecting the following: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells; creating a plurality of synthesized logic cells during said compiling, said synthesized logic cells included in said plurality of logic cells; distributing said plurality of logic cells among said plurality of gates, said synthesized logic cells being thereby distributed among said plurality of gates; and determining a subset of said plurality of gates that correspond to said line of source code; and summing the number of logic cells distributed to said subset of said plurality of gates, thereby determining the number of logic cells associated with said line of source code.
Claim 36
Dependent Claim
31 words
A computer-readable medium as recited in claim 29 wherein each of said synthesized logic cells has an output that does not correspond to any of said gates of said gate-level netlist.
Claim 37
Dependent Claim
52 words
A computer-readable medium as recited in claim 29 further comprising computer code for: grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell, whereby synthesized logic cells are taken into account during said distributing step.
Claim 38
Dependent Claim
59 words
A computer-readable medium as recited in claim 29 wherein said computer code for distributing said plurality of logic cells includes computer code for: distributing said plurality of logic cells among said plurality of gates such that the sum of all logic cells associated with said gates is equal to the number of logic cells utilized in said electronic design.
Claim 39
Dependent Claim
65 words
A computer-readable medium as recited in claim 29 wherein said computer code for summing the number of logic cells includes computer code for: summing the number of combinatorial logic cells; summing the number of registered logic cells; and summing the number of latch logic cells, whereby the number of combinatorial, registered and latch logic cells associated with said line of source code may be determined.
Claim 40
Dependent Claim
93 words
A computer-readable medium as recited in claim 29 further comprising computer code for: calculating the maximum path length through a subset of said logic cells corresponding to said subset of said plurality of gates, said subset of said plurality of gates corresponding to said line of source code of said electronic design; and providing to said designer a timing delay for said line of source code based upon said calculated maximum path length, whereby said synthesized logic cells are taken into account in determining said timing delay for said line of source code.
Claim 41
Dependent Claim
203 words
A computer-readable medium comprising computer code for providing the number of logic cells associated with a line of source code of an electronic design for a PLD, said computer code of said computer-readable medium effecting the following: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells, said plurality of logic cells including a plurality of synthesized logic cells and a plurality of hard logic cells created during said compiling; grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell; determining a number of logic cells contributing to each of said regions taking into account overlapping regions; distributing said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates; and providing a final number of logic cells associated with said line of source code to said designer based upon said distribution of said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates.
Claim 42
Dependent Claim
203 words
A computer-readable medium comprising computer code for providing the number of logic cells associated with a line of source code of an electronic design for a PLD, said computer code of said computer-readable medium effecting the following: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells, said plurality of logic cells including a plurality of synthesized logic cells and a plurality of hard logic cells created during said compiling; grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell; determining a number of logic cells contributing to each of said regions taking into account overlapping regions; distributing said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates; and providing a final number of logic cells associated with said line of source code to said designer based upon said distribution of said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates.
Claim 43
Dependent Claim
51 words
A computer-readable medium as recited in claim 35 wherein each of said synthesized logic cells has an output that does not correspond to any of said gates of said gate-level netlist, and each of said hard logic cells has an output that does correspond to a gate of said gate-level netlist.
Claim 44
Dependent Claim
87 words
A computer-readable medium as recited in claim 35 wherein said computer code for grouping said logic cells into regions includes computer code for: identifying a first hard logic cell in said post-synthesis netlist as belonging to a first region; and traversing the inputs to said first hard logic cell and including synthesized logic cells in said first region until either a hard logic cell is reached or an input pin is reached, whereby a first region of logic cells is identified that is one of said regions.
Claim 45
Dependent Claim
73 words
A computer-readable medium as recited in claim 35 wherein said computer code for distributing said number of logic cells includes computer code for: distributing said number of logic cells for each of said regions of said post-synthesis netlist among corresponding regions in said plurality of gates such that the sum of all logic cells associated with said plurality of gates is equal to the number of logic cells utilized in said electronic design.
Claim 46
Dependent Claim
66 words
A computer-readable medium as recited in claim 35 wherein said computer code for providing a final number of logic cells includes computer code for: summing the number of combinatorial logic cells; summing the number of registered logic cells; and summing the number of latch logic cells, whereby the number of combinatorial, registered and latch logic cells associated with said line of source code may be determined.
Claim 47
Dependent Claim
93 words
A computer-readable medium as recited in claim 35 further comprising computer code for: calculating the maximum path length through a subset of said logic cells corresponding to a subset of said plurality of gates, said subset of said plurality of gates corresponding to said line of source code of said electronic design; and providing to said designer a timing delay for said line of source code based upon said calculated maximum path length, whereby said synthesized logic cells are taken into account in determining said timing delay for said line of source code.
Claim 48
Dependent Claim
169 words
A computer-readable medium comprising computer code for determining a timing delay associated with a line of source code of an electronic design for a PLD, said computer code of said computer-readable medium effecting the following: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells; creating a plurality of synthesized logic cells during said compiling, said synthesized logic cells included in said plurality of logic cells; distributing said plurality of logic cells among said plurality of gates, said synthesized logic cells being thereby distributed among said plurality of gates; and determining a subset of said logic cells that correspond to said line of source code; and determining the maximum signal path length through said subset of said logic cells to provide a representation of said timing delay, whereby said synthesized logic cells are taken into account in determining said timing delay associated with said line of source code.
Claim 49
Dependent Claim
169 words
A computer-readable medium comprising computer code for determining a timing delay associated with a line of source code of an electronic design for a PLD, said computer code of said computer-readable medium effecting the following: compiling said electronic design including said line of source code to produce a gate-level netlist having a plurality of technology-independent gates and a post-synthesis netlist having a plurality of logic cells; creating a plurality of synthesized logic cells during said compiling, said synthesized logic cells included in said plurality of logic cells; distributing said plurality of logic cells among said plurality of gates, said synthesized logic cells being thereby distributed among said plurality of gates; and determining a subset of said logic cells that correspond to said line of source code; and determining the maximum signal path length through said subset of said logic cells to provide a representation of said timing delay, whereby said synthesized logic cells are taken into account in determining said timing delay associated with said line of source code.
Claim 50
Dependent Claim
31 words
A computer-readable medium as recited in claim 41 wherein each of said synthesized logic cells has an output that does not correspond to any of said gates of said gate-level netlist.
Claim 51
Dependent Claim
52 words
A computer-readable medium as recited in claim 41 further comprising computer code for: grouping said logic cells into regions such that each of said regions that includes one of said synthesized logic cells includes at least one hard logic cell, whereby synthesized logic cells are taken into account during said distributing step.
Claim 52
Dependent Claim
59 words
A computer-readable medium as recited in claim 41 wherein said computer code for distributing said plurality of logic cells includes computer code for: distributing said plurality of logic cells among said plurality of gates such that the sum of all logic cells associated with said gates is equal to the number of logic cells utilized in said electronic design.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-11-12 | 2005-05-14 | 2005-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-12 | 2009-05-14 | 2009-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-12 | 2013-05-14 | 2013-11-13 | $7700.00 | Window Closed / Lapsed |