Method and apparatus for generating variable rate synchronization signals

Claim 2

Synchronizing signal generating circuitry, for selectably providing synchronizing signals having different frequencies, comprising: a phase locked loop source of a clock signal; a divider, coupled to and external to said source, for dividing said clock signal to generate said synchronizing signals; a source of reference signal; a detector for detecting a difference between the synchronizing signal and said reference signal; selection circuitry, responsive to said difference and said synchronizing signal for conditioning said divider to divide the clock signal by a sequence of alternate divisors, wherein said divider divides said clock signal by each said alternate divisor in a sequence for no less than a period of said synchronizing signal.

Claim 3

In an MPEG-compatible compressed video signal processing apparatus, synchronizing signal generating apparatus for selectably generating synchronizing signals at different frequencies, comprising: a source of MPEG-compatible compressed video signal; an inverse transport processor including means responsive to said MPEG-compatible compressed video signal for generating a system clock signal for energizing at least in part said source and said inverse transport processor; an MPEG-compatible video signal decompressor coupled to said inverse transport processor, including means responsive to said MPEG-compatible compressed video signal for providing a control signal determinative of a frame rate decompressed said video signal is to be displayed; phase locking circuitry, responsive to said MPEG-compatible compressed video signal for generating a system clock for operating, at least in part, said inverse transport processor; a phase locked loop, coupled to said system clock for generating a pixel clock signal having a frequency higher than said system clock, for operating, at least in part, said MPEG-compatible video signal decompressor; a frequency divider, for dividing the frequency of said pixel clock to generate said synchronizing signals; and sequencing circuitry, responsive to said control signal and to generated said synchronizing signals for selecting from a plurality, greater than two, of alternative divisors, for applying selected divisors to said frequency divider, said sequencing circuitry selecting different sequences of divisors for different frequency synchronizing signals indicated by said control signal.

Claim 4

In an MPEG-compatible compressed video signal processing apparatus, synchronizing signal generating apparatus for selectably generating synchronizing signals at different frequencies, comprising: a source of MPEG-compatible compressed video signal; an inverse transport processor including means responsive to said MPEG-compatible compressed video signal for generating a system clock signal for energizing at least in part said source and said inverse transport processor; an MPEG-compatible video signal decompressor coupled to said inverse transport processor, including means responsive to said MPEG-compatible compressed video signal for providing a control signal determinative of a frame rate decompressed said video signal is to be displayed; phase locking circuitry, responsive to said MPEG-compatible compressed video signal for generating a system clock for operating, at least in part, said inverse transport processor; a phase locked loop, coupled to said system clock for generating a pixel clock signal having a frequency higher than said system clock, for operating, at least in part, said MPEG-compatible video signal decompressor; a frequency divider, for dividing the frequency of said pixel clock to generate said synchronizing signals; and sequencing circuitry, responsive to said control signal and to generated said synchronizing signals for selecting from a plurality, greater than two, of alternative divisors, for applying selected divisors to said frequency divider, said sequencing circuitry selecting different sequences of divisors for different frequency synchronizing signals indicated by said control signal.

Claim 5

The apparatus set forth in claim 2 further including circuitry for phase locking said pixel clock signal to said system clock signal.

Claim 6

The apparatus set forth in claim 3 wherein said circuitry for phase locking said pixel clock signal to said system clock signal comprises: a controlled oscillator for providing said pixel clock signal; a source of transmitted data packets, ones of which include system clock references (SCR's); circuitry for extracting said system clock references from said data packets; a modulo counter for counting pulses of said pixel clock signal or a submultiple thereof; storage means for storing count values provided by said modulo counter at predetermined instances to generate local clock references; control circuitry, responsive to said system clock references and said local clock references for generating a control signal to control said controlled oscillator; a further controlled oscillator for providing said system clock signal; a further modulo counter for counting pulses of said system clock signal or a submultiple thereof; storage means for storing count values provided by said further modulo counter at predetermined instances to generate further local clock references; and control circuitry, responsive to said system clock references and said further local clock references for generating a control signal to control said further controlled oscillator.

Claim 7

Synchronizing signal generating circuitry, for selectably providing synchronizing signals having different frequencies, comprising: a source of a clock signal having a frequency; a divider coupled to said source for dividing said clock signal frequency to generate said synchronizing signals; and sequencing circuitry, responsive to said synchronizing signals, for applying a plurality of different sequences of alternate divisors to said divider to produce different output synchronizing signal frequencies, at least some divisors being applied in repeating sequences of alternate divisors with respective divisors in a sequence being applied to said divider for at least one period of said synchronizing signal.

Claim 8

Synchronizing signal generating circuitry, for selectably providing synchronizing signals having different frequencies, comprising: a source of a clock signal having a frequency; a divider coupled to said source for dividing said clock signal frequency to generate said synchronizing signals; and sequencing circuitry, responsive to said synchronizing signals, for applying a plurality of different sequences of alternate divisors to said divider to produce different output synchronizing signal frequencies, at least some divisors being applied in repeating sequences of alternate divisors with respective divisors in a sequence being applied to said divider for at least one period of said synchronizing signal.

Claim 9

The synchronizing signal generating circuitry set forth in claim 5 wherein at least one repeating sequence includes two substantially alternating divisors and such sequence has a duration of an odd number of synchronizing signal periods.

Claim 10

The synchronizing signal generating circuitry set forth in claim 5 wherein at least one repeating sequence includes at least two alternate odd valued divisors having values in the range of 1121 to 1131 inclusive.

Claim 11

Synchronizing signal generating circuitry, for selectably providing vertical synchronizing signals having different frequencies, comprising: a source of synchronizing reference signal; a source of a clock signal frequency; a divider coupled to said source for dividing said clock signal frequency to generate said synchronizing signals; a detector, responsive to said synchronizing reference signal and said synchronizing signal for determining phase/frequency differences there between; sequencing circuitry, responsive to said synchronizing signals and said differences, for applying a plurality of alternate divisors to said divider, to produce said synchronizing signal, said sequencing circuitry having facility to cause said divider to produce different synchronizing signal output frequencies by applying different sequences of alternate divisors to said divider, and wherein respective divisors are applied to said divider for no less than one period of said synchronizing signal.

Claim 12

Synchronizing signal generating circuitry, for selectably providing vertical synchronizing signals having different frequencies, comprising: a source of synchronizing reference signal; a source of a clock signal frequency; a divider coupled to said source for dividing said clock signal frequency to generate said synchronizing signals; a detector, responsive to said synchronizing reference signal and said synchronizing signal for determining phase/frequency differences there between; sequencing circuitry, responsive to said synchronizing signals and said differences, for applying a plurality of alternate divisors to said divider, to produce said synchronizing signal, said sequencing circuitry having facility to cause said divider to produce different synchronizing signal output frequencies by applying different sequences of alternate divisors to said divider, and wherein respective divisors are applied to said divider for no less than one period of said synchronizing signal.

Claim 13

The synchronizing signal generating circuitry set forth in claim 8 wherein said sequencing circuitry includes a comparator for comparing phase signals from said detector to a plurality of different threshold values and determining sequential divisor values from the magnitude and polarity of the phase signals.

Claim 14

The synchronizing signal generating circuitry set forth in claim 8 wherein said sequencing circuitry includes a comparator for comparing phase signals from said detector to a threshold value and selects from one of first and second divisors if a phase value is less than the threshold and selects from third and fourth divisor values if the phase value does exceed said threshold value.

Claim 15

The synchronizing signal generating circuitry set forth in claim 8 wherein said source of synchronizing reference signal includes: a detector for detecting transmitted compressed digital video signal including control information; decompressor circuitry responsive to detected said compressed video signal, having an output at which said control information is available; and means for extracting said synchronizing reference signal from said control information.

Claim 16

Synchronizing signal generating circuitry, for selectably providing synchronizing signals having different frequencies, comprising a source of a clock signal; a divider coupled to said source for dividing said clock signal to generate said synchronizing signals; and circuitry for conditioning said divider to divide the clock signal by a sequence of alternate divisors; wherein said source comprises a controlled oscillator, having a control input port and an output port at which a primary clock signal is available; and a divider circuit coupled to said output port, for dividing said primary clock signal by a constant factor to provide said clock signal; wherein said controlled oscillator provides a primary clock signal of 81 Mhz, said divider circuit divides the primary clock signal by 1200, and said circuitry for conditioning said divider to divide the clock signal conditions the divider to alternately divide by 1000 and 1001.

Claim 17

Synchronizing signal generating circuitry, for selectably providing synchronizing signals having different frequencies, comprising a source of a clock signal; a divider coupled to said source for dividing said clock signal to generate said synchronizing signals; and circuitry for conditioning said divider to divide the clock signal by a sequence of alternate divisors; wherein said source comprises a controlled oscillator, having a control input port and an output port at which a primary clock signal is available; and a divider circuit coupled to said output port, for dividing said primary clock signal by a constant factor to provide said clock signal; wherein said controlled oscillator provides a primary clock signal of 81 Mhz, said divider circuit divides the primary clock signal by 1200, and said circuitry for conditioning said divider to divide the clock signal conditions the divider to alternately divide by 1000 and 1001.

Claim 20

The method set fourth in claim 13 further including selecting a set of first, second, third, and fourth divisor values from a plurality of sets of values depending upon a desired synchronizing signal frequency.

Claim 21

The method set fourth in claim 13 wherein the step of causing the frequency divider to divide said clock signal by respective selected divisors, causes division by each selected divisor for no less than a cycle of said synchronizing signal.