Patent US6297670B1 successfully refreshed from Google Patents.
← Back to Patent Explorer
US6297670B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Single-ended sense amplifier with adjustable noise margin and power down control

Assignee: Integrated Silicon Solution Inc
•
Filing: 2000-03-30
•
Granted: 2001-10-02
•
Expires: 2020-03-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The present invention discloses a single-ended sense amplifier including an output circuit having an output terminal for indicating a state of a bitline node. In addition, a noise margin circuit; and an n-channel transistor are provided for coupling or decoupling an input terminal of the output circuit with the bitline node. The variable logic-threshold inverter has a larger logic threshold voltage in response to a lower voltage level of a precharge signal and a smaller logic-threshold voltage in response to a higher voltage level of the precharge signal. The difference between the two logic-threshold voltages represents the possible noise margin. Furthermore, a power down control circuit is provided to be coupled to the bitline node for reducing the static power consumption of the single-ended sense amplifier. The single-ended sense amplifier according to the present invention provides a higher and adjustable noise margin and occupies a smaller area on a semiconductor wafer.

Inventors

  • 👤 Chin-Chieh Chao
  • 👤 Tsen-Shau Yang
  • 👤 Keh-Yung Tso

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 12:36
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/067

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 419 words
A single-ended sense amplifier for sensing a state of a first node, comprising: an output circuit having an input terminal and an output terminal, the output terminal indicating a state of the first node in response to a voltage level of the first node; a precharge circuit coupled to the input terminal for charging the input terminal in response to a first voltage level of a precharge signal; a noise margin circuit coupled to the first node for outputting a reference voltage by inverting the voltage level of the first node according to a first logic-threshold voltage in response to the first voltage level of the precharge signal and a second logic-threshold voltage in response to a second voltage level of the precharge signal; and a first n-channel transistor having a drain coupled to the input terminal of said output circuit, a source coupled to the first node, and a gate for receiving the reference voltage, and characterized in that said noise margin circuit comprises: a first p-channel transistor having a source coupled to an external voltage source, a drain coupled to the gate of said first n-channel transistor, and a gate coupled to the first node; a second n-channel transistor having a drain coupled to the gate of said first n-channel transistor, a grounded source, and a gate coupled to the first node; a second p-channel transistor having a source, a drain coupled to the gate of said first n-channel transistor, and a gate coupled to the first node; and a third p-channel transistor having a source coupled to the external voltage source, a drain coupled to the source of said second p-channel transistor, and a gate for receiving the precharge signal; wherein an inverter with the second logic-threshold voltage substantially consisting of said first p-channel transistor and said second n-channel transistor is effectively operated in response to the second voltage level of the precharge signal being higher than the first voltage level of the precharge signal by turning said second p-channel transistor and said third p-channel transistor off, and an inverter with the first logic-threshold voltage substantially consisting of said first p-channel transistor, said second n-channel transistor, said second p-channel transistor, and said third p-channel transistor is effectively operated in response to the first voltage level of the precharge signal by turning said second p-channel transistor and said third p-channel transistor on, in such a way that first logic-threshold voltage of said noise margin circuit is higher than the second logic-threshold voltage of the noise margin circuit.
Claim 2
Dependent Claim 419 words
A single-ended sense amplifier for sensing a state of a first node, comprising: an output circuit having an input terminal and an output terminal, the output terminal indicating a state of the first node in response to a voltage level of the first node; a precharge circuit coupled to the input terminal for charging the input terminal in response to a first voltage level of a precharge signal; a noise margin circuit coupled to the first node for outputting a reference voltage by inverting the voltage level of the first node according to a first logic-threshold voltage in response to the first voltage level of the precharge signal and a second logic-threshold voltage in response to a second voltage level of the precharge signal; and a first n-channel transistor having a drain coupled to the input terminal of said output circuit, a source coupled to the first node, and a gate for receiving the reference voltage, and characterized in that said noise margin circuit comprises: a first p-channel transistor having a source coupled to an external voltage source, a drain coupled to the gate of said first n-channel transistor, and a gate coupled to the first node; a second n-channel transistor having a drain coupled to the gate of said first n-channel transistor, a grounded source, and a gate coupled to the first node; a second p-channel transistor having a source, a drain coupled to the gate of said first n-channel transistor, and a gate coupled to the first node; and a third p-channel transistor having a source coupled to the external voltage source, a drain coupled to the source of said second p-channel transistor, and a gate for receiving the precharge signal; wherein an inverter with the second logic-threshold voltage substantially consisting of said first p-channel transistor and said second n-channel transistor is effectively operated in response to the second voltage level of the precharge signal being higher than the first voltage level of the precharge signal by turning said second p-channel transistor and said third p-channel transistor off, and an inverter with the first logic-threshold voltage substantially consisting of said first p-channel transistor, said second n-channel transistor, said second p-channel transistor, and said third p-channel transistor is effectively operated in response to the first voltage level of the precharge signal by turning said second p-channel transistor and said third p-channel transistor on, in such a way that first logic-threshold voltage of said noise margin circuit is higher than the second logic-threshold voltage of the noise margin circuit.
Claim 3
Dependent Claim 34 words
The sense amplifier of claim 1 , further comprising a power down control circuit coupled to the first node for pulling down the voltage of the first node in response to a power-down signal.
Claim 4
Dependent Claim 36 words
The sense amplifier of claim 2 wherein said power down control circuit comprises a third n-channel transistor having a drain coupled to the first node, a gate for receiving the power-down signal, and a grounded source.
Claim 5
Dependent Claim 84 words
The sense amplifier of claim 1 wherein said output circuit comprises: a first inverter coupled to an output node and the input terminal for sensing a state of the input terminal, respectively; a fourth p-channel transistor having a source, a drain coupled to the input terminal of said output circuit, and a gate coupled to the output node of said first inverter; and a second inverter coupled to the output node of said first inverter and the output terminal of said output circuit, respectively.
Claim 6
Dependent Claim 43 words
The sense amplifier of claim 1 wherein said precharge circuit comprises a fifth p-channel transistor having a source coupled to an external voltage source, a drain coupled to the input terminal of said output circuit, and a gate for receiving the precharge signal.
Claim 7
Dependent Claim 18 words
The sense amplifier of claim 1 wherein the first node is a bitline node in a read-only memory.
Claim 8
Dependent Claim 18 words
The sense amplifier of claim 1 wherein the first node is a bitline node in a register file.

References Cited (Backward Citations)

US5495191A Cited
US5619149A Cited
US5748015A Cited
US5689200A Cited
US5909394A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-10-01 2005-04-02 2005-10-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-10-01 2009-04-02 2009-10-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-10-01 2013-04-02 2013-10-02 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag