Patent US6289468B1 successfully refreshed from Google Patents.
US6289468B1
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Technique for controlling system bus timing with on-chip programmable delay lines
Assignee: Advanced Micro Devices Inc
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Filing: 1998-11-06
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Granted: 2001-09-11
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Expires: 2018-11-06
Abstract
Abstract An on-chip programmable delay line is provided for controlling timing of an embedded system. A delay register is coupled to a processor. The delay register stores a delay or control value responsive to the processor. The on-chip programmable delay line is coupled to the delay register and delays a signal responsive to the delay value. The relationship between dynamic random access memory (DRAM) signals, such as row address strobe (RAS) and column address strobe (CAS), can thus be adjusted. In addition, the on-chip programmable delay line can be utilized with a device that includes an input that is not synchronous to a system clock.
Inventors
- 👤 Gary M. Godfrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:10
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F5/00; G06F5/06; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C8/00; G11C8/18; G06F2205/00; G06F2205/10; G06F2205/104
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
77 words
A method of controlling component associated timing, the method comprising the steps of: determining a required delay for a signal associated with the component; setting a delay register external to the component to a delay value corresponding to the required delay; and delaying the signal with programmable delay lines that are incorporated within the component responsive to the set delay value of the delay register, wherein the delay is an analog delay independent of a system clock.
Claim 2
Independent Claim
77 words
A method of controlling component associated timing, the method comprising the steps of: determining a required delay for a signal associated with the component; setting a delay register external to the component to a delay value corresponding to the required delay; and delaying the signal with programmable delay lines that are incorporated within the component responsive to the set delay value of the delay register, wherein the delay is an analog delay independent of a system clock.
Claim 3
Dependent Claim
20 words
The method of claim 1 , wherein the component is a DRAM and the signal is a RAS memory signal.
Claim 4
Dependent Claim
20 words
The method of claim 1 , wherein the component is a DRAM and the signal is a CAS memory signal.
Claim 5
Independent Claim
50 words
An apparatus for controlling component associated timing, the apparatus comprising: a delay register external to the component for storing a delay value; and a programmable delay line for delaying a signal associated with the component responsive to the delay value, wherein the programmable delay line is incorporated within the component.
Claim 6
Independent Claim
50 words
An apparatus for controlling component associated timing, the apparatus comprising: a delay register external to the component for storing a delay value; and a programmable delay line for delaying a signal associated with the component responsive to the delay value, wherein the programmable delay line is incorporated within the component.
Claim 7
Dependent Claim
20 words
The apparatus of claim 4 , wherein the component is a DRAM and the signal is a RAS memory signal.
Claim 8
Dependent Claim
20 words
The apparatus of claim 4 , wherein the component is a DRAM and the signal is a CAS memory signal.
Claim 9
Dependent Claim
68 words
An embedded system adapted to control component associated timing, the embedded system comprising: a processor; a delay register coupled to the processor, the delay register storing a delay value responsive to the processor; and a programmable delay line coupled to the delay register, the delay line delaying a signal associated with the component responsive to the delay value, wherein the programmable delay line is incorporated within the component.
Claim 10
Dependent Claim
68 words
An embedded system adapted to control component associated timing, the embedded system comprising: a processor; a delay register coupled to the processor, the delay register storing a delay value responsive to the processor; and a programmable delay line coupled to the delay register, the delay line delaying a signal associated with the component responsive to the delay value, wherein the programmable delay line is incorporated within the component.
Claim 11
Dependent Claim
21 words
The embedded system of claim 7 , wherein the component is a DRAM and the signal is a RAS memory signal.
Claim 12
Dependent Claim
21 words
The embedded system of claim 7 , wherein the component is a DRAM and the signal is a CAS memory signal.
Claim 13
Dependent Claim
74 words
A microcontroller adapted to control component associated timing, the microcontroller comprising: a processor; a delay register coupled to the processor, the delay register storing a delay value responsive to the processor; and a programmable delay line coupled to the delay register, the delay line delaying a signal associated with the component responsive to the delay value and coupling the delayed signal to a pad, wherein the programmable delay line is incorporated within the component.
Claim 14
Dependent Claim
74 words
A microcontroller adapted to control component associated timing, the microcontroller comprising: a processor; a delay register coupled to the processor, the delay register storing a delay value responsive to the processor; and a programmable delay line coupled to the delay register, the delay line delaying a signal associated with the component responsive to the delay value and coupling the delayed signal to a pad, wherein the programmable delay line is incorporated within the component.
Claim 15
Dependent Claim
20 words
The microcontroller of claim 10 , wherein the component is a DRAM and the signal is a RAS memory signal.
Claim 16
Dependent Claim
20 words
The microcontroller of claim 10 , wherein the component is a DRAM and the signal is a CAS memory signal.
Claim 17
Dependent Claim
14 words
The microcontroller of claim 10 , wherein the signal is a programmable I/O signal.
Claim 18
Dependent Claim
14 words
The microcontroller of claim 10 , wherein the signal is a peripheral device signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-10 | 2005-03-12 | 2005-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-10 | 2009-03-12 | 2009-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-10 | 2013-03-12 | 2013-09-11 | $7700.00 | Window Closed / Lapsed |