← Back to Patent Explorer
US6288598B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Laser fuse circuit design

Assignee: Avago Technologies International Sales Pte Ltd
•
Filing: 2000-11-02
•
Granted: 2001-09-11
•
Expires: 2020-11-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A fuse circuit that includes a fuse and a full latch connected to the fuse. The fuse circuit is configured to receive a plurality of input signals including a preset signal and an enable signal. Preferably, a first pass gate is connected to the fuse and to the full latch and is configured to receive the enable signal and a second pass gate is connected to the full latch and is configured to receive the preset signal. Preferably, an output signal line is connected to the full latch and is configured to carry the output signal. The fuse circuit is configured to set the fuse using the preset signal. Ideally, the fuse circuit is configured to provide no direct path between VDD and VSS while using the preset signal to set the fuse. The fuse circuit is configured to provide an output signal which is dependent on the status of the fuse and the state of the enable signal. Specifically, the fuse circuit may be configured to provide that the output signal is of the same state as the enable signal if the fuse provides an open circuit and is configured to provide that the output signal is of a different state as the enable signal if the fuse provides a short circuit.

Inventors

  • 👤 Johnnie Huang
  • 👤 Ghasi Agrawal

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 23:43
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 78 words
A fuse circuit comprising: a fuse and a full latch connected to said fuse, said fuse circuit configured to receive a plurality of input signals including a preset signal and an enable signal, wherein said fuse circuit is configured to set said fuse using said preset signal, said fuse circuit configured to provide an output signal, wherein a value of said output signal is dependent on a status of said fuse and a state of said enable signal.
Claim 2
Dependent Claim 78 words
A fuse circuit comprising: a fuse and a full latch connected to said fuse, said fuse circuit configured to receive a plurality of input signals including a preset signal and an enable signal, wherein said fuse circuit is configured to set said fuse using said preset signal, said fuse circuit configured to provide an output signal, wherein a value of said output signal is dependent on a status of said fuse and a state of said enable signal.
Claim 3
Dependent Claim 30 words
A fuse circuit as recited in claim 1 , further comprising a pass gate connected to said fuse and to said full latch and configured to receive said enable signal.
Claim 4
Dependent Claim 26 words
A fuse circuit as recited in claim 1 , further comprising a pass gate connected to said full latch and configured to receive said preset signal.
Claim 5
Dependent Claim 48 words
A fuse circuit as recited in claim 1 , further comprising a first pass gate connected to said fuse and to said full latch and configured to receive said enable signal and a second pass gate connected to said full latch and configured to receive said preset signal.
Claim 6
Dependent Claim 27 words
A fuse circuit as recited in claim 1 , further comprising an output signal line connected to said full latch and configured to carry said output signal.
Claim 7
Dependent Claim 33 words
A fuse circuit as recited in claim 1 , wherein said fuse circuit is configured to provide no direct path between VDD and VSS while using said preset signal to set said fuse.
Claim 8
Dependent Claim 37 words
A fuse circuit as recited in claim 1 , wherein said fuse circuit is configured to provide that said output signal is of the same state as said enable signal if said fuse provides an open circuit.
Claim 9
Dependent Claim 37 words
A fuse circuit as recited in claim 1 , wherein said fuse circuit is configured to provide that said output signal is of a different state as said enable signal if said fuse provides a short circuit.
Claim 10
Dependent Claim 62 words
A fuse circuit as recited in claim 1 , wherein said fuse circuit is configured to provide that said output signal is of the same state as said enable signal if said fuse provides an open circuit and is configured to provide that said output signal is of a different state as said enable signal if said fuse provides a short circuit.
Claim 11
Dependent Claim 76 words
A fuse circuit as recited in claim 1 , further comprising a first pass gate connected to said fuse and to said full latch and configured to receive said enable signal and a second pass gate connected to said full latch and configured to receive said preset signal, wherein said fuse circuit is configured to provide that said output signal is of the same state as said enable signal if said fuse provides an open circuit.
Claim 12
Dependent Claim 76 words
A fuse circuit as recited in claim 1 , further comprising a first pass gate connected to said fuse and to said full latch and configured to receive said enable signal and a second pass gate connected to said full latch and configured to receive said preset signal, wherein said fuse circuit is configured to provide that said output signal is of a different state as said enable signal if said fuse provides a short circuit.
Claim 13
Dependent Claim 101 words
A fuse circuit as recited in claim 1 , further comprising a first pass gate connected to said fuse and to said full latch and configured to receive said enable signal and a second pass gate connected to said full latch and configured to receive said preset signal, wherein said fuse circuit is configured to provide that said output signal is of the same state as said enable signal if said fuse provides an open circuit and is configured to provide that said output signal is of a different state as said enable signal if said fuse provides a short circuit.

References Cited (Backward Citations)

US5566107A Cited
US6118712A Cited
US6215351B1 Cited
US6236599B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-09-10 2005-03-12 2005-09-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-09-10 2009-03-12 2009-09-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-09-10 2013-03-12 2013-09-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag