Slew rate control

Claim 2

An output buffer comprising: a driver circuit having an impedance that is controlled bv an impedance control signal; and a pre-driver circuit to control a slew rate of the driver circuit according to a slew rate control signal that is generated in response to the impedance control signal.

Claim 3

The output buffer of claim 1 , further comprising a compensation circuit to generate the impedance control signal to control the impedance of the driver circuit, the pre-driver circuit having elements to control the slew rate of the driver circuit to be approximately uniform during changes in the impedance of the driver circuit.

Claim 4

The output buffer of claim 1 wherein: the driver circuit includes an input capacitance dependent on the impedance of the driver circuit; and the pre-driver circuit includes elements to control the slew rate of the driver circuit based on the input capacitance of the driver circuit.

Claim 5

The output buffer of claim 3 wherein: the driver circuit includes an input and an output terminal connected to a line to drive a data signal on to the line; and the pre-driver circuit has an output coupled to the input of the driver circuit to provide the data signal to the driver circuit, the pre-driver circuit including elements to adjust a slew rate of the data signal at the input of the driver circuit to control a slew rate of the data signal at the output terminal.

Claim 6

The output buffer of claim 4 wherein the driver circuit comprises: a plurality of p-channel transistors connected in parallel between a first voltage reference and the output terminal, each p-channel transistor having a control terminal coupled to the output of the pre-driver circuit to receive a control signal based on the data signal; a plurality of n-channel transistors connected in parallel between the output terminal and a second voltage reference, each n-channel transistor having a control terminal coupled to the output of the pre-driver circuit to receive a control signal based on the data signal; and wherein the impedance of the driver circuit is determined by a number of the p-channel transistors or the n-channel transistors that are switched on and the input capacitance of the driver circuit is determined by the control terminals of the p-channel transistors or the n-channel transistors that are switched on.

Claim 7

The output buffer of claim 4 wherein the pre-driver circuit comprises: a plurality of inverters coupled in parallel between a first rail and a second rail, each inverter having an input coupled to receive the data signal and an output coupled to provide an inverted data signal to a control terminal of a transistor in the driver circuit; a plurality of first transistors coupled in parallel between a first voltage reference and the first rail, each of the first transistors having a control terminal coupled to receive a first pre-driver signal to control a state of the first transistor; and a plurality of second transistors coupled in parallel between a second voltage reference and the second rail, each of the second transistors having a control terminal coupled to receive a second pre-driver signal to control a state of the second transistor.

Claim 8

The output buffer of claim 4 , further comprising: a temperature detection circuit to detect a temperature of the output buffer; a voltage detection circuit to detect a supply voltage of the output buffer; a compensation circuit comprising: an impedance control signal generator to generate the impedance control signal based on the temperature and the supply voltage of the output buffer to substantially reduce a difference between an output impedance of the driver circuit and a characteristic impedance of the line; and a slew rate control signal generator to generate the slew rate control signal based on the temperature, the supply voltage, and the impedance control signal; and wherein the compensation circuit is coupled to provide the slew rate control signal to the pre-driver circuit and is coupled to provide the impedance control signal to the driver circuit.

Claim 9

The output buffer of claim 7 wherein: the impedance control signal comprises a plurality of impedance control signals; and the slew rate control signal generator comprises: a control voltage generator comprising: a voltage divider coupled between a first reference voltage and a second reference voltage, a control voltage line being connected to an intermediate point between the first and second reference voltages; a logic circuit coupled to receive the impedance control signals; a plurality of pull-up transistors coupled between a first reference voltage and the control voltage line, each pull-up transistor being switched on or off by one of the impedance control signals; a plurality of pull-down transistors coupled between the control voltage line and a second reference voltage, each pull-down transistor being switched on or off by one of the impedance control signals; and wherein a control voltage is generated based on the impedance control signals; and a feedback circuit to convert the control voltage into the slew rate control signal comprising a plurality of slew rate control signals, the feedback circuit comprising: a reference circuit comprising a plurality of transistors coupled in parallel between a third reference voltage and a first end of a resistor, a second end of the resistor being coupled to a fourth reference voltage; a comparator coupled to receive the control voltage at a first input and having a second input connected to the first end of the resistor; an up/down counter coupled to an output of the comparator, the up/down counter having an output from which to generate the slew rate control signals based on a comparison of the control voltage with the voltage at the first end of the resistor, the output of the up/down counter being coupled to provide the slew rate control signals respectively to the transistors in the reference circuit and to the pre-driver circuit; and wherein the slew rate control signals are generated based on the impedance control signals.

Claim 12

The system of claim 9 , further comprising a compensation circuit to generate the impedance control signal to substantially reduce a difference between an output impedance of the driver circuit and a characteristic impedance of the line, the pre-driver circuit having elements to control the slew rate of the driver circuit to be approximately uniform during changes in the output impedance of the driver circuit.

Claim 13

The system of claim 9 wherein: the driver circuit includes an input and an output terminal connected to the line to drive a data signal on to the line; and the pre-driver circuit has an output coupled to the input of the driver circuit to provide the data signal to the driver circuit, the pre-driver circuit including elements to adjust a slew rate of the data signal at the input of the driver circuit to control a slew rate of the data signal at the output terminal.

Claim 14

The system of claim 11 wherein the driver circuit comprises: a plurality of p-channel transistors connected in parallel between a first voltage reference and the output terminal, each p-channel transistor having a control terminal coupled to the output of the pre-driver circuit to receive a control signal based on the data signal and the impedance control signal; a plurality of n-channel transistors connected in parallel between the output terminal and a second voltage reference, each n-channel transistor having a control terminal coupled to the output of the pre-driver circuit to receive a control signal based on the data signal and the impedance control signal; and wherein the variable impedance of the driver circuit is determined by a number of the p-channel transistors or the n-channel transistors that are switched on.

Claim 15

The system of claim 11 wherein the pre-driver circuit comprises: a plurality of inverters coupled in parallel between a first rail and a second rail, each inverter having an input coupled to receive the data signal and an output coupled to provide an inverted data signal to a control terminal of a transistor in the driver circuit; a plurality of first transistors coupled in parallel between a first voltage reference and the first rail, each of the first transistors having a control terminal coupled to receive a first slew rate control signal to control a state of the first transistor; and a plurality of second transistors coupled in parallel between a second voltage reference and the second rail, each of the second transistors having a control terminal coupled to receive a second slew rate control signal to control a state of the second transistor.

Claim 16

The system of claim 11 , further comprising: a temperature detection circuit to detect a temperature of the system; a voltage detection circuit to detect a supply voltage of the system; a compensation circuit comprising: an impedance control signal generator to generate the impedance control signal based on the temperature and the supply voltage of the system; and a slew rate control signal generator to generate the slew rate control signal based on the temperature, the supply voltage, and the impedance control signal; and wherein the compensation circuit is coupled to provide the slew rate control signal to the pre-driver circuit and is coupled to provide the impedance control signal to the driver circuit.

Claim 17

The system of claim 14 wherein: the impedance control signal comprises a plurality of impedance control signals; and the slew rate control signal generator comprises: a control voltage generator comprising: a voltage divider coupled between a first reference voltage and a second reference voltage, a control voltage line being connected to an intermediate point between the first and second reference voltages; a logic circuit coupled to receive the impedance control signals; a plurality of pull-up transistors coupled between a first reference voltage and the control voltage line, each pull-up transistor being switched on or off by one of the impedance control signals; a plurality of pull-down transistors coupled between the control voltage line and a second reference voltage, each pull-down transistor being switched on or off by one of the impedance control signals; and wherein a control voltage is generated based on the impedance control signals; and a feedback circuit to convert the control voltage into the slew rate control signal comprising a plurality of slew rate control signals, the feedback circuit comprising: a reference circuit comprising a plurality of transistors coupled in parallel between a third reference voltage and a first end of a resistor, a second end of the resistor being coupled to a fourth reference voltage; a comparator coupled to receive the control voltage at a first input and having a second input connected to the first end of the resistor; an up/down counter coupled to an output of the comparator, the up/down counter having an output from which to generate the slew rate control signals based on a comparison of the control voltage with the voltage at the first end of the resistor, the output of the up/down counter being coupled to provide the slew rate control signals respectively to the transistors in the reference circuit and to the pre-driver circuit; and wherein the slew rate control signals are generated based on the impedance control signals.

Claim 18

The system of claim 9 , further comprising: a processor connected to the bus; a memory device connected to the bus; and an input/output device connected to the bus.

Claim 21

The method of claim 17 wherein controlling a slew rate comprises controlling a slew rate of the driver circuit to be approximately uniform during changes in the impedance of the driver circuit.

Claim 22

The method of claim 17 wherein: controlling an impedance comprises controlling an output impedance and an input capacitance of the driver circuit; and controlling a slew rate comprises controlling a slew rate of the driver circuit to be approximately uniform during changes in the input capacitance of the driver circuit.

Claim 23

The method of claim 17 wherein controlling an impedance comprises controlling an output impedance of the driver circuit to substantially reduce a difference between the output impedance and a characteristic impedance of the line.

Claim 24

The method of claim 20 wherein controlling an impedance further comprises controlling the output impedance of the driver circuit based on a temperature of the driver circuit and a supply voltage provided to the driver circuit.

Claim 25

The method of claim 17 wherein: controlling an impedance further comprises: generating the impedance control signal; and controlling a plurality of transistors coupled in parallel between a reference voltage and the line according to the impedance control signal to drive the data signal on to the line and to substantially reduce a difference between an impedance of the transistors and a characteristic impedance of the line; and controlling a slew rate further comprises: generating the slew rate control signal based on the impedance control signal; and providing the data signal to control terminals of the transistors to control the transistors based on the slew rate control signal.

Claim 28

The method of claim 23 wherein: controlling an impedance comprises controlling an output impedance and an input capacitance of the driver circuit; and controlling a slew rate comprises controlling a slew rate of the driver circuit to be approximately uniform during changes in the input capacitance of the driver circuit.

Claim 29

The method of claim 23 wherein controlling an impedance comprises controlling an output impedance of the driver circuit to substantially reduce a difference between the output impedance and a characteristic impedance of the line.

Claim 30

The method of claim 25 wherein controlling an impedance further comprises controlling the output impedance of the driver circuit based on a temperature of the driver circuit and a supply voltage provided to the driver circuit.

Claim 31

An output buffer comprising: a driver circuit having an impedance, an input capacitance dependent on the impedance, an input, and an output terminal connected to a line to drive a data signal on to the line; and a pre-driver circuit comprising: a plurality of inverters coupled in parallel between a first rail and a second rail, each inverter having an input coupled to receive the data signal and an output coupled to provide an inverted data signal to a control terminal of a transistor in the driver circuit; a plurality of first transistors coupled in parallel between a first voltage reference and the first rail, each of the first transistors having a control terminal coupled to receive a first pre-driver signal to control a state of the first transistor; a plurality of second transistors coupled in parallel between a second voltage reference and the second rail, each of the second transistors having a control terminal coupled to receive a second pre-driver signal to control a state of the second transistor; an output coupled to the input of the driver circuit to provide the data signal to the driver circuit; and wherein the inverters, the first transistors, and the second transistors are coupled to adjust a slew rate of the data signal at the input of the driver circuit based on the input capacitance of the driver circuit to control a slew rate of the data signal at the output terminal.

Claim 32

An output buffer comprising: a driver circuit having an impedance, an input capacitance dependent on the impedance, an input, and an output terminal connected to a line to drive a data signal on to the line; and a pre-driver circuit comprising: a plurality of inverters coupled in parallel between a first rail and a second rail, each inverter having an input coupled to receive the data signal and an output coupled to provide an inverted data signal to a control terminal of a transistor in the driver circuit; a plurality of first transistors coupled in parallel between a first voltage reference and the first rail, each of the first transistors having a control terminal coupled to receive a first pre-driver signal to control a state of the first transistor; a plurality of second transistors coupled in parallel between a second voltage reference and the second rail, each of the second transistors having a control terminal coupled to receive a second pre-driver signal to control a state of the second transistor; an output coupled to the input of the driver circuit to provide the data signal to the driver circuit; and wherein the inverters, the first transistors, and the second transistors are coupled to adjust a slew rate of the data signal at the input of the driver circuit based on the input capacitance of the driver circuit to control a slew rate of the data signal at the output terminal.

Claim 33

An output buffer comprising: a driver circuit having an impedance, an input capacitance dependent on the impedance, an input, and an output terminal connected to a line to drive a data signal on to the line; a pre-driver circuit having an output coupled to the input of the driver circuit to provide the data signal to the driver circuit, the pre-driver circuit including elements to adjust a slew rate of the data signal at the input of the driver circuit based on the input capacitance of the driver circuit to control a slew rate of the data signal at the output terminal; a temperature detection circuit to detect a temperature of the output buffer; a voltage detection circuit to detect a supply voltage of the output buffer; a compensation circuit comprising: an impedance control signal generator to generate an impedance control signal based on the temperature and the supply voltage of the output buffer to substantially reduce a difference between an output impedance of the driver circuit and a characteristic impedance of the line; and a slew rate control signal generator to generate a slew rate control signal based on the temperature, the supply voltage, and the impedance control signal; and wherein the compensation circuit is coupled to provide the slew rate control signal to the pre-driver circuit and is coupled to provide the impedance control signal to the driver circuit.

Claim 34

An output buffer comprising: a driver circuit having an impedance, an input capacitance dependent on the impedance, an input, and an output terminal connected to a line to drive a data signal on to the line; a pre-driver circuit having an output coupled to the input of the driver circuit to provide the data signal to the driver circuit, the pre-driver circuit including elements to adjust a slew rate of the data signal at the input of the driver circuit based on the input capacitance of the driver circuit to control a slew rate of the data signal at the output terminal; a temperature detection circuit to detect a temperature of the output buffer; a voltage detection circuit to detect a supply voltage of the output buffer; a compensation circuit comprising: an impedance control signal generator to generate an impedance control signal based on the temperature and the supply voltage of the output buffer to substantially reduce a difference between an output impedance of the driver circuit and a characteristic impedance of the line; and a slew rate control signal generator to generate a slew rate control signal based on the temperature, the supply voltage, and the impedance control signal; and wherein the compensation circuit is coupled to provide the slew rate control signal to the pre-driver circuit and is coupled to provide the impedance control signal to the driver circuit.

Claim 35

The output buffer of claim 28 wherein: the impedance control signal comprises a plurality of impedance control signals; and the slew rate control signal generator comprises: a control voltage generator comprising: a voltage divider coupled between a first reference voltage and a second reference voltage, a control voltage line being connected to an intermediate point between the first and second reference voltages; a logic circuit coupled to receive the impedance control signals; a plurality of pull-up transistors coupled between a first reference voltage and the control voltage line, each pull-up transistor being switched on or off by one of the impedance control signals; a plurality of pull-down transistors coupled between the control voltage line and a second reference voltage, each pull-down transistor being switched on or off by one of the impedance control signals; and wherein a control voltage is generated based on the impedance control signals; and a feedback circuit to convert the control voltage into the slew rate control signal comprising a plurality of slew rate control signals, the feedback circuit comprising: a reference circuit comprising a plurality of transistors coupled in parallel between a third reference voltage and a first end of a resistor, a second end of the resistor being coupled to a fourth reference voltage; a comparator coupled to receive the control voltage at a first input and having a second input connected to the first end of the resistor; an up/down counter coupled to an output of the comparator, the up/down counter having an output from which to generate the slew rate control signals based on a comparison of the control voltage with the voltage at the first end of the resistor, the output of the up/down counter being coupled to provide the slew rate control signals respectively to the transistors in the reference circuit and to the pre-driver circuit; and wherein the slew rate control signals are generated based on the impedance control signals.

Claim 40

The system of claim 31 wherein: the impedance control signal comprises a plurality of impedance control signals; and the slew rate control signal generator comprises: a control voltage generator comprising: a voltage divider coupled between a first reference voltage and a second reference voltage, a control voltage line being connected to an intermediate point between the first and second reference voltages; a logic circuit coupled to receive the impedance control signals; a plurality of pull-up transistors coupled between a first reference voltage and the control voltage line, each pull-up transistor being switched on or off by one of the impedance control signals; a plurality of pull-down transistors coupled between the control voltage line and a second reference voltage, each pull-down transistor being switched on or off by one of the impedance control signals; and wherein a control voltage is generated based on the impedance control signals; and a feedback circuit to convert the control voltage into the slew rate control signal comprising a plurality of slew rate control signals, the feedback circuit comprising: a reference circuit comprising a plurality of transistors coupled in parallel between a third reference voltage and a first end of a resistor, a second end of the resistor being coupled to a fourth reference voltage; a comparator coupled to receive the control voltage at a first input and having a second input connected to the first end of the resistor; an up/down counter coupled to an output of the comparator, the up/down counter having an output from which to generate the slew rate control signals based on a comparison of the control voltage with the voltage at the first end of the resistor, the output of the up/down counter being coupled to provide the slew rate control signals respectively to the transistors in the reference circuit and to the pre-driver circuit; and wherein the slew rate control signals are generated based on the impedance control signals.