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Method for forming a capacitor using tantalum nitride as a capacitor dielectric

Assignee: SK Hynix Inc
•
Filing: 2000-12-22
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Granted: 2001-09-11
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Expires: 2020-12-22
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Abstract

Abstract A method for fabricating capacitors for semiconductor devices utilizing a Ta 3 N 5 dielectric layer is provided by the present invention. This method includes the steps of forming a lower electrode on a semiconductor substrate, depositing an amorphous TaON thin film over the lower electrode, and subjecting the deposited amorphous TaON thin film to a thermal process in an NH 3 atmosphere, thereby forming a Ta 3 N 5 dielectric film, and forming an upper electrode on the Ta 3 N 5 dielectric film. The resulting Ta 3 N 5 dielectric film provides a dielectric constant significantly greater than those that can be achieved with conventional dielectric films. Accordingly, the Ta 3 N 5 dielectric film of the present invention can be used to manufacture capacitors for the next generation semiconductor memory devices of 256M grade or higher.

Inventors

  • 👤 Kee Jeung Lee
  • 👤 Hong Seon Yang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 09:27
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/01; H10D1/041; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10D1/682; H10D1/684; H10D1/692; H10D1/711; H10D1/712; H10D1/716; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69393

Claims Analysis

Total Claims: 23
Claim 1
Independent Claim 65 words
A method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming a lower electrode on a semiconductor substrate; forming an amorphous TaON thin film over the lower electrode, annealing the amorphous TaON thin film in an NH 3 atmosphere to produce a Ta 3 N 5 dielectric film; and forming an upper electrode on the Ta 3 N 5 dielectric film.
Claim 2
Independent Claim 65 words
A method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming a lower electrode on a semiconductor substrate; forming an amorphous TaON thin film over the lower electrode, annealing the amorphous TaON thin film in an NH 3 atmosphere to produce a Ta 3 N 5 dielectric film; and forming an upper electrode on the Ta 3 N 5 dielectric film.
Claim 3
Dependent Claim 101 words
The method according to claim 1 , wherein the step of forming the lower electrode further comprises forming at least a first lower conductive layer, the first lower conductive layer comprising doped polysilicon or metal and, optionally, forming a second lower conductive layer, the second lower conductive layer comprising doped polysilicon or metal; and further wherein the step of forming the upper electrode further comprises forming at least a first upper conductive layer, the first upper conductive layer comprising doped polysilicon or metal and, optionally, forming a second upper conductive layer, the second upper conductive layer comprising doped polysilicon or metal.
Claim 4
Dependent Claim 30 words
The method according to claim 2 , wherein the metal is selected from the group consisting of TiN, Ti, TaN, W, WN, WSi, Ru, RuO 2 , Ir, and Pt.
Claim 5
Dependent Claim 37 words
The method according to claim 1 , wherein the step of forming the lower electrode further comprises forming a layer of doped polysilicon, the layer of doped polysilicon having a surface characterized by a hemispherical grain structure.
Claim 6
Dependent Claim 40 words
The method according to claim 1 , wherein the step of forming the lower electrode further comprises forming a layer of doped polysilicon and nitriding the layer of doped polysilicon in an NH 3 atmosphere for 1 to 5 minutes.
Claim 7
Dependent Claim 65 words
The method according to claim 1 , the step of forming an amorphous TaON thin film over the lower electrode further comprising etching the surface of the lower electrode to remove a native oxide, the etching step comprising a dry cleaning process using HF vapor or a wet cleaning process using an HF solution, and then depositing a TaON thin film on the lower electrode.
Claim 8
Dependent Claim 29 words
The method according to claim 1 , wherein the step of annealing the amorphous TaON thin film is carried out at a temperature of between 600 and 950° C.
Claim 9
Dependent Claim 48 words
The method according to claim 1 , wherein the step of forming the amorphous TaON thin film further comprises evaporating a tantalum compound at a temperature between 150 and 200° C. to produce a tantalum compound vapor and injecting the resulting tantalum compound vapor into a LPCVD chamber.
Claim 10
Dependent Claim 59 words
The method according to claim 8 , wherein the step of forming the amorphous TaON thin film further comprises controlling the injecting of the tantalum compound vapor with a mass flow controller, injecting NH 3 into the LPCVD chamber, and maintaining the LPCVD chamber at a temperature between 300 and 600° C. and at a pressure below 100 Torr.
Claim 11
Dependent Claim 31 words
The method according to claim 1 , further comprising the step of treating the Ta 3 N 5 dielectric film to control the final nitrogen content in the Ta3N5 dielectric film.
Claim 12
Dependent Claim 66 words
The method according to claim 10 , wherein the step of treating the Ta3N5 dielectric film comprises subjecting the Ta 3 N 5 dielectric film to at least a plasma process under an O 2 or N 2 O atmosphere, a rapid thermal process under an O 2 or N 2 O atmosphere, or an annealing process under an O 3 atmosphere with optional UV radiation.
Claim 13
Dependent Claim 36 words
The method according to claim 11 , wherein the step of treating the Ta 3 N 5 dielectric film further comprises the step of forming an oxide film over the Ta 3 N 5 dielectric film.
Claim 14
Dependent Claim 37 words
The method according to claim 1 , wherein the step of annealing the amorphous TaON thin film further comprises using a rapid thermal process or a electric furnace, the furnace being operated at or below atmospheric pressure.
Claim 15
Dependent Claim 24 words
The method according to claim 13 , further comprising the step of forming an oxide film over the Ta 3 N 5 dielectric film.
Claim 16
Independent Claim 86 words
A method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming a lower electrode on a semiconductor substrate; forming an amorphous TaON thin film over the lower electrode, and subjecting the amorphous TaON thin film to a thermal process under an NH 3 atmosphere at a temperature between 600 and 950° C., to form a Ta 3 N 5 dielectric film; annealing the Ta 3 N 5 dielectric film; and forming an upper electrode on the Ta 3 N 5 dielectric film.
Claim 17
Independent Claim 86 words
A method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming a lower electrode on a semiconductor substrate; forming an amorphous TaON thin film over the lower electrode, and subjecting the amorphous TaON thin film to a thermal process under an NH 3 atmosphere at a temperature between 600 and 950° C., to form a Ta 3 N 5 dielectric film; annealing the Ta 3 N 5 dielectric film; and forming an upper electrode on the Ta 3 N 5 dielectric film.
Claim 18
Dependent Claim 51 words
The method according to claim 15 , wherein the annealing step further comprises a plasma process under an O 2 or N 2 O atmosphere, a rapid thermal process under an O 2 or N 2 O atmosphere, or an annealing process under an O 3 atmosphere with optional UV radiation.
Claim 19
Dependent Claim 128 words
The method according to claim 15 , wherein the step of forming lower forming the lower electrode further comprises forming at least a first lower conductive layer, the first lower conductive layer comprising doped polysilicon or metal and, optionally, forming a second lower conductive layer, the second lower conductive layer comprising doped polysilicon or metal; and further wherein the step of forming the upper electrode further comprises forming at least a first upper conductive layer, the first upper conductive layer comprising doped polysilicon or metal and, optionally, forming a second upper conductive layer, the second upper conductive layer comprising doped polysilicon or metal; and further wherein the metal is selected from a group consisting of TiN, Ti, TaN, W, WN, WSi, Ru, RuO 2 , Ir, and Pt.
Claim 20
Dependent Claim 37 words
The method according to claim 15 , wherein the step of forming the lower electrode further comprises forming a layer of doped polysilicon, the layer of doped polysilicon having a surface characterized by a hemispherical grain structure.
Claim 21
Dependent Claim 40 words
The method according to claim 15 , wherein the step of forming the lower electrode further comprises forming a layer of doped polysilicon and nitriding the layer of doped polysilicon in an NH 3 atmosphere for 1 to 5 minutes.
Claim 22
Independent Claim 94 words
A method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming a lower electrode on a semiconductor substrate; nitriding the lower electrode in an NH 3 atmosphere; forming an amorphous TaON thin film over the lower electrode, subjecting the amorphous TaON thin film to a thermal process in an NH 3 atmosphere at a temperature between 600 and 950° C., to form a Ta 3 N 5 dielectric film; annealing the Ta 3 N 5 dielectric film; and forming an upper electrode on the Ta 3 N 5 dielectric film.
Claim 23
Independent Claim 94 words
A method for fabricating a capacitor of a semiconductor device, comprising the steps of: forming a lower electrode on a semiconductor substrate; nitriding the lower electrode in an NH 3 atmosphere; forming an amorphous TaON thin film over the lower electrode, subjecting the amorphous TaON thin film to a thermal process in an NH 3 atmosphere at a temperature between 600 and 950° C., to form a Ta 3 N 5 dielectric film; annealing the Ta 3 N 5 dielectric film; and forming an upper electrode on the Ta 3 N 5 dielectric film.

References Cited (Backward Citations)

US5352623A Cited
US6201276B1 Cited
JP2000058878A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-09-10 2005-03-12 2005-09-11 $2000.00 Window Closed / Lapsed
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