US6285574B1
Expired / Lapsed
US
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Symmetric segmented memory array architecture
Assignee: Spansion Israel Ltd
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Filing: 1999-07-06
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Granted: 2001-09-04
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Expires: 2019-07-06
Abstract
Abstract A symmetric memory array includes a multiplicity of repeating segments formed into rows and columns. Each segment includes a cell area formed of four segmented cell bit lines an even select area and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment. The array additionally includes one even contact connected to the even contact bit lines of two neighboring even select areas, one odd contact connected to the odd contact bit lines of two neighboring odd select areas and alternating even and odd metal lines connecting to the even and odd contacts, respectively.
Inventors
- 👤 Boaz Eitan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:09
CPC Classifications
H; H10; H10B; H10B69/00; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/0475; G11C16/0491; G11C7/00; G11C7/18; H10D; H10D89/00; H10D89/10; G11C16/06; G11C16/24
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
359 words
A memory array comprising: a plurality of groups of memory cells, each group of memory cells comprising: a first bit line, a second bit line, a third bit line, and a fourth bit line; a first metal line and a second metal line for allowing selected voltages to be supplied to said first, second, third, and fourth bit lines; a first two-terminal select transistor and a second two-terminal select transistor, wherein a first terminal of each first and second select transistor is electrically connected to said first metal line; a third two-terminal select transistor and a fourth two-terminal select transistor, wherein a first terminal of each third and fourth select transistor is electrically connected to said second metal line; first, second, third, and fourth material electrically connecting a second terminal of each of said first, said second, said third, and said fourth select transistors to said first, said third, said second, and said fourth bits lines, respectively; first, second, third, and fourth select lines for supplying selected voltages to a conductive gate of each of said first, said second, said third, and said fourth select transistors respectively; a first plurality of memory cells connected between said first, and second bit lines, a second plurality of memory cells connected between said second and third bit lines, a third plurality of memory cells connected between said third and fourth bit lines, and a fourth plurality of memory cells connected between said fourth bit line and a fifth bit line, wherein said fifth bit line is a first bit line in a next group of memory cells in a same row, or is an extra bit line adjacent a last group of memory cells in the same row; wherein said array is configured such that to write to, read, or erase a selected memory cell in said first, said second, said third, or said fourth plurality of memory cells, selected voltages are supplied to said first and said second metal lines, and a combination of said first, second, third, and fourth select transistors is turned on to pass the voltages on said first and second metal lines to said selected memory cell.
Claim 2
Dependent Claim
359 words
A memory array comprising: a plurality of groups of memory cells, each group of memory cells comprising: a first bit line, a second bit line, a third bit line, and a fourth bit line; a first metal line and a second metal line for allowing selected voltages to be supplied to said first, second, third, and fourth bit lines; a first two-terminal select transistor and a second two-terminal select transistor, wherein a first terminal of each first and second select transistor is electrically connected to said first metal line; a third two-terminal select transistor and a fourth two-terminal select transistor, wherein a first terminal of each third and fourth select transistor is electrically connected to said second metal line; first, second, third, and fourth material electrically connecting a second terminal of each of said first, said second, said third, and said fourth select transistors to said first, said third, said second, and said fourth bits lines, respectively; first, second, third, and fourth select lines for supplying selected voltages to a conductive gate of each of said first, said second, said third, and said fourth select transistors respectively; a first plurality of memory cells connected between said first, and second bit lines, a second plurality of memory cells connected between said second and third bit lines, a third plurality of memory cells connected between said third and fourth bit lines, and a fourth plurality of memory cells connected between said fourth bit line and a fifth bit line, wherein said fifth bit line is a first bit line in a next group of memory cells in a same row, or is an extra bit line adjacent a last group of memory cells in the same row; wherein said array is configured such that to write to, read, or erase a selected memory cell in said first, said second, said third, or said fourth plurality of memory cells, selected voltages are supplied to said first and said second metal lines, and a combination of said first, second, third, and fourth select transistors is turned on to pass the voltages on said first and second metal lines to said selected memory cell.
Claim 3
Dependent Claim
340 words
A memory array comprising: a first bit line and a second bit line each having a first end and a second end; a plurality of memory cells connected between said first and second bit lines, wherein one memory cell in said plurality of memory cells is connected between said first end of said bit line and said first end of said second bit line, and another memory cell in said plurality of memory cells is connected between said second end of said first bit line and said second end of said second bit line; a first metal line; a second metal line; a first select transistor including a first terminal, a second terminal, and a conductive gate, wherein said first terminal of said first select transistor is connected to said first metal line and said second terminal of said first select transistor is connected to said second end of said first bit line; a second select transistor including a first terminal, a second terminal, and a conductive gate, wherein said first terminal of said second select transistor is connected to said second metal line and said second terminal of said second select transistor is connected to said first end of said second bit line; a plurality of word lines, wherein each word line is said plurality of word lines is connected to a corresponding unique memory cell in said plurality of memory cells so as to allow a voltage to be applied to said corresponding unique memory cell sufficient to permit said corresponding unique memory cell to be written to, read or, erased; a first select line electrically connected to said gate of said first select transistor; and a second select line electrically connected to said gate of said second select transistor; wherein said array is configured such that when said unique memory cell is selected to be written to, read, or erased, the electrical path from said first metal line to said second metal line has substantially constant electrical resistance regardless of the location of said unique memory cell.
Claim 4
Dependent Claim
340 words
A memory array comprising: a first bit line and a second bit line each having a first end and a second end; a plurality of memory cells connected between said first and second bit lines, wherein one memory cell in said plurality of memory cells is connected between said first end of said bit line and said first end of said second bit line, and another memory cell in said plurality of memory cells is connected between said second end of said first bit line and said second end of said second bit line; a first metal line; a second metal line; a first select transistor including a first terminal, a second terminal, and a conductive gate, wherein said first terminal of said first select transistor is connected to said first metal line and said second terminal of said first select transistor is connected to said second end of said first bit line; a second select transistor including a first terminal, a second terminal, and a conductive gate, wherein said first terminal of said second select transistor is connected to said second metal line and said second terminal of said second select transistor is connected to said first end of said second bit line; a plurality of word lines, wherein each word line is said plurality of word lines is connected to a corresponding unique memory cell in said plurality of memory cells so as to allow a voltage to be applied to said corresponding unique memory cell sufficient to permit said corresponding unique memory cell to be written to, read or, erased; a first select line electrically connected to said gate of said first select transistor; and a second select line electrically connected to said gate of said second select transistor; wherein said array is configured such that when said unique memory cell is selected to be written to, read, or erased, the electrical path from said first metal line to said second metal line has substantially constant electrical resistance regardless of the location of said unique memory cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-03 | 2005-03-05 | 2005-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-03 | 2009-03-05 | 2009-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-03 | 2013-03-05 | 2013-09-04 | $7700.00 | Window Closed / Lapsed |