← Back to Patent Explorer
US6284623B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect

Assignee: Newport Fab LLC
•
Filing: 1999-10-25
•
Granted: 2001-09-04
•
Expires: 2019-10-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of fabricating semiconductor devices, such as conductors, fuses, capacitors, diodes, transistors, and the like, includes forming or obtaining a semiconductor wafer having a substrate material, an oxide layer, and a nitride layer. Mesas (the edges of which include active regions) are then formed by etching trenches (gaps) into the substrate material through the nitride and oxide layers. In accordance with one aspect of the present invention, the nitride layer is then pulled-back or retracted from the edges of the active regions thus exposing the corners of the active regions. The gaps and the edges of the active regions are then lined with a layer of oxide which rounds the corners of the active regions. The gaps are filled with another layer of oxide, and the semiconductor wafer is then planarized. Optionally, the edges of the active regions are then implanted with dopant.

Inventors

  • 👤 Peng-Fei Zhang
  • 👤 Richard A. Mann

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 10:48
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 35
Claim 1
Independent Claim 108 words
A method of fabricating a semiconductor device on a wafer having a layer of substrate material, a first layer of oxide on top of the layer of substrate material, and a layer of nitride on top of the layer of oxide, said method comprising the steps of: etching a plurality of trenches through the layer of nitride and the first layer of oxide and into the layer of substrate material to form mesas between said trenches, wherein said mesas have edges; retracting the layer of nitride from the edges of said mesas; and after said retracting, forming a second layer of oxide on the edges of the mesas.
Claim 2
Independent Claim 108 words
A method of fabricating a semiconductor device on a wafer having a layer of substrate material, a first layer of oxide on top of the layer of substrate material, and a layer of nitride on top of the layer of oxide, said method comprising the steps of: etching a plurality of trenches through the layer of nitride and the first layer of oxide and into the layer of substrate material to form mesas between said trenches, wherein said mesas have edges; retracting the layer of nitride from the edges of said mesas; and after said retracting, forming a second layer of oxide on the edges of the mesas.
Claim 3
Dependent Claim 31 words
The method of claim 1 , wherein said etching step further comprises the step of masking the trenches using DUV lithography; and wherein the trenches are etched using reactive ion etching.
Claim 4
Dependent Claim 26 words
The method of claim 1 , wherein said plurality of trenches extends between about 2500 Angstroms and about 3500 Angstroms into the layer of substrate material.
Claim 5
Dependent Claim 14 words
The method of claim 3 , wherein the layer of substrate material comprises silicon.
Claim 6
Dependent Claim 23 words
The method of claim 1 , wherein said retracting step comprises the step of immersing the wafer in a hot phosphoric acid bath.
Claim 7
Dependent Claim 29 words
The method of claim 1 , wherein said retracting step retracts the layer of nitride to between about 250 Angstroms and 500 Angstroms from the edges of the mesas.
Claim 8
Dependent Claim 25 words
The method of claim 1 , wherein said forming step comprises the step of forming the second layer of oxide using a thermal oxidation process.
Claim 9
Dependent Claim 33 words
The method of claim 1 , further comprising the steps of: filling the trenches with a third layer of oxide; planarizing the wafer; and implanting a dopant into the edges of the mesas.
Claim 10
Dependent Claim 16 words
The method of claim 8 , wherein said filling step comprises depositing high density plasma oxide.
Claim 11
Dependent Claim 14 words
The method of claim 8 , wherein said planarizing step comprises chemical mechanical planarization.
Claim 12
Dependent Claim 24 words
The method of claim 8 , wherein said implanting step comprises ion implantation at between about 15 kilo electron-volts and about 250 kilo electron-volts.
Claim 13
Dependent Claim 12 words
The method of claim 8 , wherein said dopant comprises Boron ions.
Claim 14
Dependent Claim 12 words
The method of claim 8 , wherein said dopant comprises Phosphorous ions.
Claim 15
Dependent Claim 29 words
The method of claim 1 , further comprising the step of depositing a third layer of oxide on top of the layer of nitride prior to said etching step.
Claim 16
Dependent Claim 15 words
The method of claim 14 , wherein said third layer of oxide comprises TEOS oxide.
Claim 17
Dependent Claim 21 words
The method of claim 14 , wherein said etching step etches said plurality of trenches through said third layer of oxide.
Claim 18
Dependent Claim 27 words
The method of claim 16 , further comprising the step of removing said third layer of oxide following said retracting step and prior to said depositing step.
Claim 19
Independent Claim 104 words
A method of fabricating a semiconductor device using a semiconductor wafer having a substrate material layer, said method comprising the steps of: depositing a pad oxide layer on top of said substrate material layer; depositing a pad nitride layer on top of said pad oxide layer; etching a plurality of trenches through said pad nitride layer and said pad oxide layer and into said substrate material layer to form mesas between said trenches, wherein said mesas have edges; retracting said pad nitride layer from the edges of said mesas; and after said retracting, depositing a liner oxide layer on the edges of said mesas.
Claim 20
Independent Claim 104 words
A method of fabricating a semiconductor device using a semiconductor wafer having a substrate material layer, said method comprising the steps of: depositing a pad oxide layer on top of said substrate material layer; depositing a pad nitride layer on top of said pad oxide layer; etching a plurality of trenches through said pad nitride layer and said pad oxide layer and into said substrate material layer to form mesas between said trenches, wherein said mesas have edges; retracting said pad nitride layer from the edges of said mesas; and after said retracting, depositing a liner oxide layer on the edges of said mesas.
Claim 21
Dependent Claim 21 words
The method of claim 18 , wherein said wafer comprises a P-type silicon wafer and said substrate material layer comprises silicon.
Claim 22
Dependent Claim 22 words
The method of claim 18 , wherein said pad oxide layer is between about 100 Angstroms and about 150 Angstroms in thickness.
Claim 23
Dependent Claim 22 words
The method of claim 18 , wherein said pad nitride layer is between about 1,100 Angstroms and about 2,000 Angstroms in thickness.
Claim 24
Dependent Claim 26 words
The method of claim 18 , wherein said plurality of trenches extends between about 2500 Angstroms and about 3500 Angstroms into the layer of substrate material.
Claim 25
Dependent Claim 38 words
The method of claim 18 , wherein said step of depositing rounds the corners of the layer of substrate material of the mesas such that the radii of the corners is about 50 nanometers to about 100 nanometers.
Claim 26
Dependent Claim 33 words
The method of claim 18 , further comprising the steps of: depositing a filler oxide layer to fill-in said trenches; planarizing the wafer; and implanting a dopant into the edges of the mesas.
Claim 27
Dependent Claim 29 words
The method of claim 24 , wherein said retracting step retracts said pad nitride layer to between about 250 Angstroms and 500 Angstroms from the edges of the mesas.
Claim 28
Dependent Claim 24 words
The method of claim 24 , wherein said implanting step comprises ion implanting at between about 15 kilo electron-volts and about 250 kilo electron-volts.
Claim 29
Dependent Claim 28 words
The method of claim 24 , further comprising the step of depositing a TEOS oxide layer on top of said pad nitride layer prior to said etching step.
Claim 30
Dependent Claim 22 words
The method of claim 27 , wherein said TEOS oxide layer is between about 300 Angstroms and about 500 Angstroms in thickness.
Claim 31
Dependent Claim 20 words
The method of claim 27 , further comprising the step of removing said TEOS oxide layer following said retracting step.
Claim 32
Independent Claim 126 words
A method of fabricating a semiconductor device using a semiconductor wafer having a substrate material layer, said method comprising the steps of: depositing a pad oxide layer on top of said substrate material layer; depositing a pad nitride layer on top of said pad oxide layer; etching a plurality of trenches through said pad nitride layer and said pad oxide layer and into said substrate material layer to form mesas between said trenches, wherein said mesas have edges; retracting said pad nitride layer from the edges of said mesas; after said retracting, depositing a liner oxide layer on the edges of said mesas; depositing a filler oxide layer to fill in said trenches; planarizing the wafer; and implanting a dopant into the edges of the mesas.
Claim 33
Independent Claim 126 words
A method of fabricating a semiconductor device using a semiconductor wafer having a substrate material layer, said method comprising the steps of: depositing a pad oxide layer on top of said substrate material layer; depositing a pad nitride layer on top of said pad oxide layer; etching a plurality of trenches through said pad nitride layer and said pad oxide layer and into said substrate material layer to form mesas between said trenches, wherein said mesas have edges; retracting said pad nitride layer from the edges of said mesas; after said retracting, depositing a liner oxide layer on the edges of said mesas; depositing a filler oxide layer to fill in said trenches; planarizing the wafer; and implanting a dopant into the edges of the mesas.
Claim 34
Dependent Claim 28 words
The method of claim 30 , further comprising the step of depositing a TEOS oxide layer on top of said pad nitride layer prior to said etching step.
Claim 35
Dependent Claim 20 words
The method of claim 31 , further comprising the step of removing said TEOS oxide layer following said retracting step.

References Cited (Backward Citations)

US4923821A Cited
US5872058A Cited
US6143635A Cited
US5989978A Cited
US5960276A Cited
US6156906A Cited
US6225187B1 Cited
US6228727B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-09-03 2005-03-05 2005-09-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-09-03 2009-03-05 2009-09-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-09-03 2013-03-05 2013-09-04 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag