Semiconductor integrated circuit having a clock recovery circuit

Claim 2

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: an input standard node, to which said external clock is coupled, for supplying a first standard clock; a plurality of first delay circuits, whose initial stage is coupled to said input standard node, for supplying a plurality of reference clocks differing in phase from each other; a control circuit having a comparator for detecting a predetermined number of delay stages required for locking in by comparing the plurality of reference clocks with said first standard clock and detecting one of the plurality of reference clocks closest in phase to said first standard clock, and a latch circuit for holding information on said predetermined number of delay stages; a plurality of second delay circuits each having an input node into which said first standard clock is entered via a switch; and an output standard node which is coupled to the final stage of said second delay circuits, and which supplies said internal clock, and wherein said internal clock is formed by causing said first standard clock to be entered into said input node of one of said plurality of second delay circuits which corresponds to said predetermined number of delay stages detected by said control circuit, and to be propagated to the final stage.

Claim 3

A semiconductor integrated circuit according to claim 1 , wherein after said latch circuit has held the information on said predetermined number of delay stages, the entry of said first standard clock into said plurality of first delay circuits and said comparator is suspended.

Claim 4

A semiconductor integrated circuit according to claim 1 , wherein when the supply of said external clock to said clock recovery circuit is suspended for a predetermined period after said latch circuit has held the information on said predetermined number of delay stages, and said external clock is supplied again, said plurality of second delay circuits forms said internal clock in accordance with information on said predetermined number of delay stages held by said latch circuit.

Claim 5

A semiconductor integrated circuit according to claim 1 , wherein after said latch circuit has latched said predetermined number of delay stages, the supply of working power to said plurality of first delay circuits and to said comparator of said control circuit is suspended.

Claim 6

A semiconductor integrated circuit according to claim 1 , wherein said semiconductor integrated circuit further has a second clock recovery circuit, wherein said second clock recovery circuit has a variable delay circuit inserted between said plurality of second delay circuits and the output node of said internal clock, and a phase comparator for comparing the phases of said first standard clock and of said internal clock and controlling the delay time of said variable delay circuit, and wherein the delay time of each of the pluralities of first and second delay circuits of said first clock recovery circuit is a first delay time, and wherein the unit of varying the delay time by said variable delay circuit is a second delay time shorter than said first delay time.

Claim 7

A semiconductor integrated circuit according to claim 5 , wherein said second delay time is about {fraction (1/10)} of said first delay time.

Claim 8

A semiconductor integrated circuit according to claim 5 , wherein the operation of said phase comparator of said second clock recovery circuit is suspended before said latch circuit holds said predetermined number of delay stages, and wherein said phase comparator is enabled to operate and the entry of said external clock into said plurality of first delay circuits and said comparator is suspended after said latch circuit has held said predetermined number of delay stages.

Claim 9

A semiconductor integrated circuit according to claim 5 , wherein after said latch circuit has latched said predetermined number of delay stages, the supply of working power to said plurality of first delay circuits and to said comparator is suspended.

Claim 10

A semiconductor integrated circuit according to claim 5 , wherein said second clock recovery circuit further comprises a control signal generating circuit which receives first and second signals supplied by said phase comparator, and supplies a shift register control signal, and a shift register which receives said shift register control signal, and controls said variable delay circuit, and wherein said shift register is controlled according to the output of said phase comparator.

Claim 11

A semiconductor integrated circuit according to claim 5 , wherein a bit other than the least significant bit and the most significant bit is set in said shift register at the time of initial setting.

Claim 12

A semiconductor integrated circuit according to claim 10 , wherein said shift register is controlled by a binary search algorithm.

Claim 13

A semiconductor integrated circuit according to claim 1 , wherein said clock recovery circuit is further provided with a shot pulse generator, which receives said external clock, narrows the pulse width and supplies the resultant clock to said standard node as said first standard clock, a plurality of third delay circuits in which delay circuits in a number equal to ½ of the number of said plurality of second delay circuits are connected in series, and a logic circuit inserted between the output end of said plurality of second delay circuits and said output standard node, and wherein said logic circuit forms said internal clock having a frequency double that of said external clock by logical summation of a first clock resulting from the entry of said first standard clock into the input nodes of said plurality of second delay circuits corresponding to said predetermined number of delay stages detected by said control circuit, and of a second clock resulting from the entry of said first standard clock into the input nodes of said plurality of third delay circuits corresponding to half of said predetermined number of delay stages detected by said control circuit, and supplying the resultant logical sum to said output standard node.

Claim 14

A semiconductor integrated circuit according to claim 1 , wherein said clock recovery circuit further receives, in addition to said external clock, an inverted external clock having an inverted phase relative to said external clock and generates said internal clock, wherein said clock recovery circuit further comprises: a first shot pulse generator which receives said external clock, narrows the pulse width and supplies the resultant clock to said standard node as said first standard clock; a second shot pulse generator which receives said inverted external clock, narrows the pulse width and supplies a second standard clock; a plurality of third delay circuits each provided correspondingly to said plurality of second delay circuits; and a logic circuit inserted between the final stage of said plurality of second delay circuits and said output standard node, and wherein said logic circuit forms said internal clock having a frequency double that of said external clock by logical summation of a first clock resulting from the entry of said first standard clock into one of said input nodes of said plurality of second delay circuits corresponding to said predetermined number of delay stages detected by said control circuit, and of a second clock resulting from the entry of said second standard clock into the input nodes of said plurality of third delay circuits corresponding to said predetermined number of delay stages detected by said control circuit, and supplying the resultant logical sum to said output standard node.

Claim 15

A semiconductor integrated circuit according to claim 1 , wherein said clock recovery circuit further receives, in addition to said external clock, an inverted external clock having an inverted phase relative to said external clock and generates said internal clock, wherein said clock recovery circuit further comprises: a first shot pulse generator which receives said external clock, and generates a first clock whose pulse width is narrowed; a second shot pulse generator which receives said inverted external clock, and generates a second clock whose pulse width is narrowed; and a logic circuit for supplying said standard node with a signal resulting from the logical summation of said first and second clocks as said first standard clock, and wherein said internal clock has a frequency double that of said external clock.

Claim 16

A semiconductor integrated circuit according to claim 1 , wherein said semiconductor integrated circuit further has an address input circuit into which an address is entered according to said external clock; a plurality of memory cells selected by said address; and a memory with clock synchronized interface for supplying read data from said plurality of memory cells according to said internal clock.

Claim 17

A semiconductor integrated circuit having a clock recovery circuit which receives a first external clock and a second external clock having an inverted phase relative to said first external clock and which generates an internal clock having a frequency double that of said first external clock, wherein said clock recovery circuit comprises: a first shot pulse generator which receives said external clock, and supplies a first clock whose pulse width is narrowed, a second shot pulse generator which receives said inverted external clock, and supplies a second clock whose pulse width is narrowed; a logic circuit for generating a third clock resulting from the logical summation of said first and second clocks; a plurality of first delay circuits which receive said first clock and which supply a plurality of reference clocks differing in phase from each other; a control circuit having a comparator for detecting a predetermined number of delay stages required for locking in by comparing said plurality of reference clocks with said first clock and detecting the reference clock closest in phase to said first clock, and a latch circuit for holding information on said predetermined number of delay stages; and a plurality of second delay circuits each having an input node into which said third clock is entered via a switch, wherein said internal clock is formed by causing said third clock to be entered into a selected one of said input nodes of said plurality of second delay circuits which corresponds to said predetermined number of delay stage detected by said control circuit, and to be propagated to a final stage of said second delay circuits.

Claim 18

A semiconductor integrated circuit having a clock recovery circuit which receives a first external clock and a second external clock having an inverted phase relative to said first external clock and which generates an internal clock having a frequency double that of said first external clock, wherein said clock recovery circuit comprises: a first shot pulse generator which receives said external clock, and supplies a first clock whose pulse width is narrowed, a second shot pulse generator which receives said inverted external clock, and supplies a second clock whose pulse width is narrowed; a logic circuit for generating a third clock resulting from the logical summation of said first and second clocks; a plurality of first delay circuits which receive said first clock and which supply a plurality of reference clocks differing in phase from each other; a control circuit having a comparator for detecting a predetermined number of delay stages required for locking in by comparing said plurality of reference clocks with said first clock and detecting the reference clock closest in phase to said first clock, and a latch circuit for holding information on said predetermined number of delay stages; and a plurality of second delay circuits each having an input node into which said third clock is entered via a switch, wherein said internal clock is formed by causing said third clock to be entered into a selected one of said input nodes of said plurality of second delay circuits which corresponds to said predetermined number of delay stage detected by said control circuit, and to be propagated to a final stage of said second delay circuits.

Claim 19

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: an input buffer, which receives said external clock, for supplying a standard clock from a first node; a first delay circuit array having a first input node coupled to said first node; a plurality of first delay circuits connected in series, whose input end is coupled to said first input node; and a plurality of first output nodes. provided in each of the connecting nodes of said plurality of first delay circuits, for supplying a plurality of second clocks; a control circuit having a second input node coupled to said first node; a plurality of reference signal input nodes coupled to said plurality of first output nodes; and a plurality of reference result output nodes; a second delay circuit array having a third input node coupled to said first node; a plurality of control signal input nodes coupled to said plurality of reference result output nodes; a plurality of second delay circuits connected in series, each provided correspondingly to said plurality of control input nodes; and a second output node coupled to the output of the final stage of said plurality of second delay circuits; a second node coupled to said second output node; and an output buffer circuit. coupled to said second node, for supplying said internal clock, and wherein said control circuit compares the phases of said first clock entered into said second input node with that of a plurality of clock signals entered into said plurality of reference signal input nodes from said first delay circuit array, detects as the lock-in stage one of said plurality of reference signal nodes into which the closest one of said plurality of clock signals in phase; and supplies a predetermined signal for the lock-in stare to one of a plurality of comparison result output nodes corresponding to said lock-in stage, and wherein said second delay circuit array enters said standard clock into one of said plurality of second delay circuits corresponding to said plurality of control signal input nodes into which said predetermined signal for the lock-in stage is entered, causing the clock to propagate through a predetermined number of said second delay circuits, and supplying it to said second output node; wherein said control circuit further includes a plurality of latch circuits each coupled to one of said plurality of comparison result output nodes, and wherein said plurality of latch circuits hold information on said stage for lock-in.

Claim 20

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: an input buffer, which receives said external clock, for supplying a standard clock from a first node; a first delay circuit array having a first input node coupled to said first node; a plurality of first delay circuits connected in series, whose input end is coupled to said first input node; and a plurality of first output nodes. provided in each of the connecting nodes of said plurality of first delay circuits, for supplying a plurality of second clocks; a control circuit having a second input node coupled to said first node; a plurality of reference signal input nodes coupled to said plurality of first output nodes; and a plurality of reference result output nodes; a second delay circuit array having a third input node coupled to said first node; a plurality of control signal input nodes coupled to said plurality of reference result output nodes; a plurality of second delay circuits connected in series, each provided correspondingly to said plurality of control input nodes; and a second output node coupled to the output of the final stage of said plurality of second delay circuits; a second node coupled to said second output node; and an output buffer circuit. coupled to said second node, for supplying said internal clock, and wherein said control circuit compares the phases of said first clock entered into said second input node with that of a plurality of clock signals entered into said plurality of reference signal input nodes from said first delay circuit array, detects as the lock-in stage one of said plurality of reference signal nodes into which the closest one of said plurality of clock signals in phase; and supplies a predetermined signal for the lock-in stare to one of a plurality of comparison result output nodes corresponding to said lock-in stage, and wherein said second delay circuit array enters said standard clock into one of said plurality of second delay circuits corresponding to said plurality of control signal input nodes into which said predetermined signal for the lock-in stage is entered, causing the clock to propagate through a predetermined number of said second delay circuits, and supplying it to said second output node; wherein said control circuit further includes a plurality of latch circuits each coupled to one of said plurality of comparison result output nodes, and wherein said plurality of latch circuits hold information on said stage for lock-in.

Claim 21

A semiconductor integrated circuit according to claim 17 , wherein the entry of said standard clock into said plurality of first delay circuits and said control circuit is suspended after said plurality of latch circuits have held information on said stage for lock-in.

Claim 22

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: an input buffer, which receives said external clock, for supplying a standard clock from a first node; a first delay circuit array having a first input node coupled to said first node; a plurality of first delay circuits connected in series, whose input end is coupled to said first input node; and a plurality of first output nodes, provided in each of the connecting nodes of said plurality of first delay circuits, for supplying a plurality of second clocks; a control circuit having a second input node coupled to said first node; a plurality of reference signal input nodes coupled to said plurality of first output nodes; and a plurality of reference result output nodes; a second delay circuit array having a third input node coupled to said first node; a plurality of control signal input nodes coupled to said plurality of reference result output nodes; a plurality of second delay circuits connected in series, each provided correspondingly to said plurality of control input nodes; and a second output node coupled to the output of the final stage of said plurality of second delay circuits; a second node coupled to said second output node; and an output buffer circuit, coupled to said second node, for supplying said internal clock, and wherein said control circuit compares the phases of said first clock entered into said second input node with that of a plurality of clock signals entered into said plurality of reference signal input nodes from said first delay circuit array. detects as the lock-in stage one of said plurality of reference signal nodes into which the closest one of said plurality of clock signals in phase; and supplies a predetermined signal for the lock-in stage to one of a plurality of comparison result output nodes corresponding to said lock-in stage, and wherein said second delay circuit array enters said standard clock into one of said plurality of second delay circuits corresponding to said plurality of control signal input nodes into which said predetermined signal for the lock-in stage is entered, causing the clock to propagate through a predetermined number of said second delay circuits, and supplying it to said second output node; wherein said semiconductor integrated circuit further has said second clock recovery circuit, wherein said second clock recovery circuit has a phase comparator for comparing the phases of said standard clock and of said internal clock supplied by said output buffer, and a variable delay circuit inserted between said second node and the input end of said output buffer, and adjusting the delay time with a first delay time as the unit according to the result of comparison by said phase comparator, wherein each of the pluralities of first and second delay circuits of said first clock recovery circuit has a second delay time, and wherein said second delay time is longer than said first delay time.

Claim 23

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: an input buffer, which receives said external clock, for supplying a standard clock from a first node; a first delay circuit array having a first input node coupled to said first node; a plurality of first delay circuits connected in series, whose input end is coupled to said first input node; and a plurality of first output nodes, provided in each of the connecting nodes of said plurality of first delay circuits, for supplying a plurality of second clocks; a control circuit having a second input node coupled to said first node; a plurality of reference signal input nodes coupled to said plurality of first output nodes; and a plurality of reference result output nodes; a second delay circuit array having a third input node coupled to said first node; a plurality of control signal input nodes coupled to said plurality of reference result output nodes; a plurality of second delay circuits connected in series, each provided correspondingly to said plurality of control input nodes; and a second output node coupled to the output of the final stage of said plurality of second delay circuits; a second node coupled to said second output node; and an output buffer circuit, coupled to said second node, for supplying said internal clock, and wherein said control circuit compares the phases of said first clock entered into said second input node with that of a plurality of clock signals entered into said plurality of reference signal input nodes from said first delay circuit array. detects as the lock-in stage one of said plurality of reference signal nodes into which the closest one of said plurality of clock signals in phase; and supplies a predetermined signal for the lock-in stage to one of a plurality of comparison result output nodes corresponding to said lock-in stage, and wherein said second delay circuit array enters said standard clock into one of said plurality of second delay circuits corresponding to said plurality of control signal input nodes into which said predetermined signal for the lock-in stage is entered, causing the clock to propagate through a predetermined number of said second delay circuits, and supplying it to said second output node; wherein said semiconductor integrated circuit further has said second clock recovery circuit, wherein said second clock recovery circuit has a phase comparator for comparing the phases of said standard clock and of said internal clock supplied by said output buffer, and a variable delay circuit inserted between said second node and the input end of said output buffer, and adjusting the delay time with a first delay time as the unit according to the result of comparison by said phase comparator, wherein each of the pluralities of first and second delay circuits of said first clock recovery circuit has a second delay time, and wherein said second delay time is longer than said first delay time.

Claim 24

A semiconductor integrated circuit according to claim 19 , wherein the variable delay circuit includes a plurality of inverter circuits connected in series, of which the input end is coupled to said second node and the output end is coupled to the input end of said output buffer, wherein each of said plurality of inverter circuits includes a plurality of first MISFETs of a first conductivity type whose sources and drains are connected in parallel, a second MISFET of a first conductivity type, a third MISFET of a second conductivity type, and a plurality of fourth MISFETs of a second conductivity type, each paired with one of said plurality of first MISFETs, whose sources and drains are connected in parallel, wherein said first, second, third, and fourth MISFETs, have sources and drains which are connected in series, wherein the gates of said second and third MISFETs are made input ends, and the coupling nodes of said second and third MISFETs are made output ends, and wherein each of said plurality of fourth MISFETs and the one of said plurality of first MISFETs paired with it differ from each other in gate size.

Claim 25

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: a plurality of first delay circuits, to which said external clock is coupled, for supplying a plurality of reference clocks differing in phase from each other; a control circuit having a comparator for detecting a predetermined number of delay stages required for locking in by comparing the plurality of reference clocks with said external clock and detecting the reference clock closest in phase to said clock, and a latch circuit for holding information on said predetermined number of delay stages; and a plurality of second delay circuits for supplying said internal clock resulting from the delaying of said external clock correspondingly to said predetermined number of delay stages detected by said control circuit, said external clock being inputted to one of said plurality of second delay circuits corresponding to said predetermined number of delay stages.

Claim 26

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: a plurality of first delay circuits, to which said external clock is coupled, for supplying a plurality of reference clocks differing in phase from each other; a control circuit having a comparator for detecting a predetermined number of delay stages required for locking in by comparing the plurality of reference clocks with said external clock and detecting the reference clock closest in phase to said clock, and a latch circuit for holding information on said predetermined number of delay stages; and a plurality of second delay circuits for supplying said internal clock resulting from the delaying of said external clock correspondingly to said predetermined number of delay stages detected by said control circuit, said external clock being inputted to one of said plurality of second delay circuits corresponding to said predetermined number of delay stages.

Claim 27

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: an input standard node, to which said external clock is coupled, which supplies a first standard clock; a plurality of first delay circuits, whose initial stage is coupled to said input standard node, which supply a plurality of reference clocks differing in phase from each other; a control circuit having a comparator which detects a predetermined number of delay stages required for locking in by comparing the plurality of reference clocks with said first standard clock and detecting one of the plurality of reference clocks closest in phase to said first standard clock, and a latch circuit which holds information on said predetermined number of delay stages; a plurality of second delay circuits each having an input node to receive said first standard clock via a switch; and an output standard node which is coupled to the final stage of said second delay circuits, and which supplies said internal clock, and wherein said internal clock is formed by causing said first standard clock to be entered into said input node of one of said plurality of second delay circuits which corresponds to said predetermined number of delay stages detected by said control circuit, and to be propagated to the final stage.

Claim 28

A semiconductor integrated circuit having a clock recovery circuit which receives an external clock and generates an internal clock, wherein said clock recovery circuit comprises: an input standard node, to which said external clock is coupled, which supplies a first standard clock; a plurality of first delay circuits, whose initial stage is coupled to said input standard node, which supply a plurality of reference clocks differing in phase from each other; a control circuit having a comparator which detects a predetermined number of delay stages required for locking in by comparing the plurality of reference clocks with said first standard clock and detecting one of the plurality of reference clocks closest in phase to said first standard clock, and a latch circuit which holds information on said predetermined number of delay stages; a plurality of second delay circuits each having an input node to receive said first standard clock via a switch; and an output standard node which is coupled to the final stage of said second delay circuits, and which supplies said internal clock, and wherein said internal clock is formed by causing said first standard clock to be entered into said input node of one of said plurality of second delay circuits which corresponds to said predetermined number of delay stages detected by said control circuit, and to be propagated to the final stage.