Clock converting circuit

Claim 2

A clock converting circuit for converting a primary clock signal having any duty ratio to a secondary clock signal having a duty ratio of (1/2 K )×100%, where K is a natural number, said circuit comprising: a pulse generating circuit for generating a first pulse signal having the same cycle as, and a duration different from, the primary clock signal; a cycle measuring circuit for measuring a cycle of the first clock pulse signal, which is approximately m times a unit time, the cycle measuring circuit having a plurality of first delay elements connected in cascade; a number converting circuit for multiplying m by 1/2 K ; a time converting circuit for generating a second pulse signal having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a time which is m/2 K times the unit time, the time converting circuit having a plurality of second delay elements connected in cascade, each of said second delay elements corresponding to two or more first delay elements; and a logic circuit for generating the second clock signal from the first pulse signal and the second pulse signal, said secondary clock signal rising in synchronism with the first pulse signal and falling in synchronism with the second pulse signal.

Claim 3

A clock converting circuit according to claim 1, wherein the first and second delay elements have a delay time equal to the unit time.

Claim 4

A clock converting circuit according to claim 2, wherein the first delay elements and the second delay elements are arranged on a semiconductor chip, and the cascade of the second delay elements extends parallel to the cascade of the first delay elements.

Claim 5

A clock converting circuit according to claim 3, wherein the second delay elements are arranged to transfer signals in a direction opposite to a direction in which the first delay elements transfer signals.

Claim 6

A clock converting circuit according to claim 3, wherein the second delay elements are provided in a number 1/2 K times the number of the first delay elements.

Claim 7

A clock converting circuit according to claim 3, wherein each of the second delay elements is associated with adjacent 2 K first delay elements and connected thereto by the number converting circuit.

Claim 8

A clock converting circuit according to claim 3, wherein the number converting circuit has pulse output circuits in the same number as the second delay elements, and each of the pulse output circuit is connected to outputs of adjacent 2 K first delay elements and an output of the pulse generating circuit, for outputting a pulse to an associated one of the second delay elements when an output of any one of the adjacent 2 K first delay elements and the first pulse signal output from the pulse generating circuit are at logic "1" level.

Claim 9

A clock converting circuit according to claim 7, further comprising a pulse-duration modulating circuit for modulating a duration of the first pulse signal and supplying to the pulse output circuits the first pulse signal having a duration modulated.

Claim 10

A clock converting circuit according to claim 8, wherein the pulse-duration modulating circuit modulates the duration of the first pulse signal so that the sum of the modulated duration of the first pulse signal and the duration of a pulse output from any first delay element is greater than the unit time.

Claim 11

A clock converting circuit according to claim 8, wherein the pulse-duration modulating circuit modulates the duration of the first pulse signal so that the modulated duration of the first pulse signal is less than the unit time.

Claim 12

A clock converting circuit according to claim 7, further comprising a plurality of dummy load elements connected to the outputs of the second delay elements, respectively, and having a capacitance equal to the difference between the input capacitance and output capacitance of each pulse output circuit.

Claim 13

A clock converting circuit for converting a primary clock signal having any duty ratio to a secondary clock signal having a duty ratio of (1/2 K )×100% and to a tertiary clock signal having a duty ratio of (1/2 K+1 )×100%, where K is a natural number, said circuit comprising: a pulse generating circuit for generating a first pulse signal having the same cycle as, and a duration different from, the primary clock signal; a cycle measuring circuit for measuring a cycle of the first clock pulse signal, which is approximately m times a unit time; a first number converting circuit for multiplying m by 1/2 K ; a second number converting circuit for multiplying m by 1/2 K+1 ; first time converting circuit for generating a second pulse signal having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a time which is m/2 K times the unit time; second time converting circuit for generating a third pulse signal having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a time which is m/2 K+1 times the unit time; a first logic circuit for generating the secondary clock signal from the first pulse signal and the second pulse signal, said secondary clock signal rising in synchronism with the first pulse signal and falling in synchronism with the second pulse signal; and a second logic circuit for generating the tertiary clock signal from the first pulse signal and the third pulse signal, said tertiary clock signal rising in synchronism with the first pulse signal and falling in synchronism with the third pulse signal.

Claim 14

A clock converting circuit for converting a primary clock signal having any duty ratio to a secondary clock signal having a duty ratio of (1/2 K )×100% and to a tertiary clock signal having a duty ratio of (1/2 K+1 )×100%, where K is a natural number, said circuit comprising: a pulse generating circuit for generating a first pulse signal having the same cycle as, and a duration different from, the primary clock signal; a cycle measuring circuit for measuring a cycle of the first clock pulse signal, which is approximately m times a unit time; a first number converting circuit for multiplying m by 1/2 K ; a second number converting circuit for multiplying m by 1/2 K+1 ; first time converting circuit for generating a second pulse signal having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a time which is m/2 K times the unit time; second time converting circuit for generating a third pulse signal having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a time which is m/2 K+1 times the unit time; a first logic circuit for generating the secondary clock signal from the first pulse signal and the second pulse signal, said secondary clock signal rising in synchronism with the first pulse signal and falling in synchronism with the second pulse signal; and a second logic circuit for generating the tertiary clock signal from the first pulse signal and the third pulse signal, said tertiary clock signal rising in synchronism with the first pulse signal and falling in synchronism with the third pulse signal.

Claim 15

A clock converting circuit for converting a primary clock signal having any duty ratio to a secondary clock signal which is in phase with the primary clock signal and which has a duty ratio of (1/2 K )×100%, where K is a natural number, said circuit comprising: a pulse generating circuit for generating a first pulse signal having the same cycle as the primary clock signal and delayed by a first delay time with respect to the primary clock signal; a delay circuit for delaying the first pulse signal by twice a second delay time, thereby generating a second pulse signal; a cycle measuring circuit for measuring a period between the first pulse signal and the second pulse signal, which is m times a unit time; a number converting circuit for multiplying m by 1/2 K ; time converting circuit for generating a third pulse signal having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a time which is m times the unit time; a circuit for generating a fourth pulse having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a difference between the cycle of the first pulse signal and the second delay time; a logic circuit for generating the secondary clock signal from the third pulse signal and the fourth pulse signal, said secondary clock signal rising in synchronism with the fourth pulse signal and falling in synchronism with the third pulse signal; and a buffer for outputting the secondary clock signal, said buffer having such a delay time that a sum of the delay time of the logic circuit, the delay time of the buffer and the first delay time is substantially equal to the second delay time.

Claim 16

A clock converting circuit for converting a primary clock signal having any duty ratio to a secondary clock signal which is in phase with the primary clock signal and which has a duty ratio of (1/2 K )×100%, where K is a natural number, said circuit comprising: a pulse generating circuit for generating a first pulse signal having the same cycle as the primary clock signal and delayed by a first delay time with respect to the primary clock signal; a delay circuit for delaying the first pulse signal by twice a second delay time, thereby generating a second pulse signal; a cycle measuring circuit for measuring a period between the first pulse signal and the second pulse signal, which is m times a unit time; a number converting circuit for multiplying m by 1/2 K ; time converting circuit for generating a third pulse signal having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a time which is m times the unit time; a circuit for generating a fourth pulse having substantially the same cycle as the first pulse signal and delayed with respect to the first pulse signal by a difference between the cycle of the first pulse signal and the second delay time; a logic circuit for generating the secondary clock signal from the third pulse signal and the fourth pulse signal, said secondary clock signal rising in synchronism with the fourth pulse signal and falling in synchronism with the third pulse signal; and a buffer for outputting the secondary clock signal, said buffer having such a delay time that a sum of the delay time of the logic circuit, the delay time of the buffer and the first delay time is substantially equal to the second delay time.

Claim 17

A clock converting circuit circuit for converting a primary clock signal having any duty ratio to a secondary clock signal having a duty ratio of 50%, said circuit comprising: a pulse generating circuit for generating a first pulse signal having the same cycle as, and a duration different from, the primary clock signal; an N number of first delay elements connected to an output of the pulse generating circuit, and connected in cascade; an (N/2) number of pulse output circuits, each connected to outputs of two adjacent first delay elements and the output of the pulse generating circuit, for generating a pulse when an output of any one of the two adjacent first delay elements and an output of the pulse generating circuit are at logic level "1"; an (N/2) number of second delay elements connected to outputs of the pulse output circuits, respectively, connected in cascade and having substantially the same delay time as the first delay elements, the pulse signal output from each of the pulse output circuits being output through m/2 second delays as a second pulse signal, where m is the number of first delay elements associated with the pulse signal output from each of the pulse output circuits; a logic circuit for generating the secondary clock signal from the first pulse signal and the second pulse signal, said secondary clock signal rising in synchronism with the first pulse signal and falling in synchronism with the second pulse signal.

Claim 18

A clock converting circuit circuit for converting a primary clock signal having any duty ratio to a secondary clock signal having a duty ratio of 50%, said circuit comprising: a pulse generating circuit for generating a first pulse signal having the same cycle as, and a duration different from, the primary clock signal; an N number of first delay elements connected to an output of the pulse generating circuit, and connected in cascade; an (N/2) number of pulse output circuits, each connected to outputs of two adjacent first delay elements and the output of the pulse generating circuit, for generating a pulse when an output of any one of the two adjacent first delay elements and an output of the pulse generating circuit are at logic level "1"; an (N/2) number of second delay elements connected to outputs of the pulse output circuits, respectively, connected in cascade and having substantially the same delay time as the first delay elements, the pulse signal output from each of the pulse output circuits being output through m/2 second delays as a second pulse signal, where m is the number of first delay elements associated with the pulse signal output from each of the pulse output circuits; a logic circuit for generating the secondary clock signal from the first pulse signal and the second pulse signal, said secondary clock signal rising in synchronism with the first pulse signal and falling in synchronism with the second pulse signal.