Duration-sensitive digital signal gate

Claim 1

A duration-sensitive signal gate for use with a clocked source of signals alternatively exhibiting a "1" or a "0" level, comprising: delay means having a plurality of successive signal takeoff points; the amount of delay between successive ones of said takeoff points being the same; the input of said delay means being responsive to the output of said signal source; a plurality of signal paths, each connected to a respectively different one of said signal takeoff points; an "and" gate having a plurality of inputs equal in number to said plurality of signal paths, each of said signal paths terminating at a respectively different one of said plurality of inputs of said "and" gate; a plurality of delay devices, each imparting the same predetermined amount of delay; and a succession of two-input "or" gates, each associated with a respectively different one of said plurality of delay devices, with one input of each of said succession rendered responsive to the output of said "and" gate, and with the other input of each of said succession coupled to the output of the associated one of said plurality of delay devices; means for supplying the output of the last of said succession of "or" gates to an output terminal; means for delivering the output of each of the remainder of said succession of "or" gates to the input of the delay device associated with the next succeeding one of said succession; and means for rendering the input of the delay device associated with the first of said succession of "or" gates responsive only to the output of said "and" gate.