Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill

Claim 1

A method to form transistor gates and shallow trench isolations in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; depositing a pad oxide layer overlying said semiconductor substrate; depositing a silicon nitride layer overlying said pad oxide layer; patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations; depositing a photoresist layer overlying said silicon nitride layer and filling said trenches; etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled; patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning; removing said photoresist layer; thereafter depositing a dielectric layer overlying said dummy gates and said trenches; polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer; etching away said dummy gates to form openings for said planned transistor gate electrodes; depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode; and polishing down said gate electrode layer to form said transistor gates and to complete said integrated circuit device.

Claim 2

A method to form transistor gates and shallow trench isolations in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; depositing a pad oxide layer overlying said semiconductor substrate; depositing a silicon nitride layer overlying said pad oxide layer; patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations; depositing a photoresist layer overlying said silicon nitride layer and filling said trenches; etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled; patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning; removing said photoresist layer; thereafter depositing a dielectric layer overlying said dummy gates and said trenches; polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer; etching away said dummy gates to form openings for said planned transistor gate electrodes; depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode; and polishing down said gate electrode layer to form said transistor gates and to complete said integrated circuit device.

Claim 11

A method to form MOS transistors with shallow trench isolations in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; depositing a pad oxide layer overlying said semiconductor substrate; depositing a silicon nitride layer overlying said pad oxide layer; patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations; depositing a photoresist layer overlying said silicon nitride layer and filling said trenches; implanting ions into said semiconductor substrate to form transistor well junctions; etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled; patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning; implanting ions into said semiconductor substrate to form lightly doped drain junctions; forming sidewall spacers on said dummy gate electrodes; implanting ions into said semiconductor substrate to form source and drain junctions; removing said photoresist layer; thereafter depositing a dielectric layer overlying said dummy gates and said trenches; polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer; etching away said dummy gates to form openings for said planned transistor gate electrodes; depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode; and polishing down said gate electrode layer to form said transistor gates and to form said transistors and to complete said integrated circuit device.

Claim 12

A method to form MOS transistors with shallow trench isolations in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; depositing a pad oxide layer overlying said semiconductor substrate; depositing a silicon nitride layer overlying said pad oxide layer; patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations; depositing a photoresist layer overlying said silicon nitride layer and filling said trenches; implanting ions into said semiconductor substrate to form transistor well junctions; etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled; patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning; implanting ions into said semiconductor substrate to form lightly doped drain junctions; forming sidewall spacers on said dummy gate electrodes; implanting ions into said semiconductor substrate to form source and drain junctions; removing said photoresist layer; thereafter depositing a dielectric layer overlying said dummy gates and said trenches; polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer; etching away said dummy gates to form openings for said planned transistor gate electrodes; depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode; and polishing down said gate electrode layer to form said transistor gates and to form said transistors and to complete said integrated circuit device.

Claim 20

A method to form MOS transistors with shallow trench isolations in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; depositing a pad oxide layer overlying said semiconductor substrate; depositing a silicon nitride layer overlying said pad oxide layer; patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations; oxidizing said trenches to form an oxide layer on the inside surfaces of said trenches; depositing a photoresist layer overlying said silicon nitride layer and filling said trenches; implanting ions into said semiconductor substrate to form transistor well junctions; etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled; patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning; implanting ions into said semiconductor substrate to form lightly doped drain junctions; forming sidewall spacers on said dummy gate electrodes; implanting ions into said semiconductor substrate to form source and drain junctions; removing said photoresist layer; thereafter depositing a dielectric layer overlying said dummy gates and said trenches wherein said dielectric layer comprises a silicon dioxide deposited by a high density plasma process; polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer; etching away said dummy gates to form openings for said planned transistor gate electrodes; depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode; and polishing down said gate electrode layer to form said transistor gates and to form said transistors and to complete said integrated circuit device.

Claim 21

A method to form MOS transistors with shallow trench isolations in the manufacture of an integrated circuit device comprising: providing a semiconductor substrate; depositing a pad oxide layer overlying said semiconductor substrate; depositing a silicon nitride layer overlying said pad oxide layer; patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations; oxidizing said trenches to form an oxide layer on the inside surfaces of said trenches; depositing a photoresist layer overlying said silicon nitride layer and filling said trenches; implanting ions into said semiconductor substrate to form transistor well junctions; etching down said photoresist layer to below the top surface of said silicon nitride layer the trench remaining filled; patterning said silicon nitride layer and said pad oxide layer to form dummy gates where said transistor gates are planned and wherein the presence of said photoresist layer protects said trenches from patterning; implanting ions into said semiconductor substrate to form lightly doped drain junctions; forming sidewall spacers on said dummy gate electrodes; implanting ions into said semiconductor substrate to form source and drain junctions; removing said photoresist layer; thereafter depositing a dielectric layer overlying said dummy gates and said trenches wherein said dielectric layer comprises a silicon dioxide deposited by a high density plasma process; polishing down said dielectric layer to the top surface of said dummy gates to thereby form said shallow trench isolations and to form a planarized interlevel dielectric layer; etching away said dummy gates to form openings for said planned transistor gate electrodes; depositing a gate electrode layer overlying said dielectric layer and filling said openings for said planned transistor gate electrode; and polishing down said gate electrode layer to form said transistor gates and to form said transistors and to complete said integrated circuit device.