US6274450B1
Expired / Lapsed
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Method for implementing metal oxide semiconductor field effect transistor
Assignee: United Microelectronics Corp
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Filing: 1999-09-17
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Granted: 2001-08-14
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Expires: 2019-09-17
Abstract
Abstract A method for manufacturing metal oxide semiconductor field effect transistor is disclosed. The metal oxide semiconductor field effect transistor is formed by a specific fabricating process that disadvantages of thermal damage are effectively prevented. According to the method, first a substrate is provided. Second, an isolation and a well are formed in the substrate, and then a first dielectric layer, a conductive layer and an anti-reflection coating layer are formed on the substrate sequentially. Third, a gate is formed on the substrate, and then a source and a drain are formed in the substrate and a spacer is formed on the substrate. Fourth, both source and drain are annealed, and then a first salicide is formed on both source and drain. Fifth, a second dielectric layer is formed on the substrate and is planarized, where the anti-reflecting coating layer is totally removed and the conductive layer is partially removed. Sixth, a second salicide is formed on the conductive layer. Seventh, the spacer is removed and both a halo and a source drain extension are formed in substrate. Finally, a third dielectric layer is formed on second dielectric layer. Obviously, one main characteristic of the invention is both source drain extension and halo are formed after a plurality of thermal processes such as deposition, annealing and formation of salicide.
Inventors
- 👤 Tony Lin
- 👤 Coming Chen
- 👤 Jih-Wen Chou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0213; H10D30/022; H10D64/00; H10D64/01; H10D64/015; H10D64/017; H10D64/60; H10D64/66; H10D64/667; H10D64/671; H10D64/675; H10D64/679
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
217 words
A method for manufacturing a metal oxide semiconductor field effect transistor, said method comprising steps of: providing a substrate; forming an isolation in said substrate; forming a well in said substrate, wherein said well is enclosed by said isolation; forming a first dielectric layer on said substrate; forming a conductive layer on said first dielectric layer; forming an anti-reflection coating layer on said conductive layer; removing portions of said anti-reflection coating layer, said conductive layer and said first dielectric layer to form a gate; forming a source and a drain in said substrate around said gate; forming a spacer on a sidewall of said gate; annealing said source and said drain; forming a first salicide on said source and said drain; forming a second dielectric layer on said substrate, wherein said second dielectric layer totally covers said gate and said spacer; planarizing said second dielectric layer, wherein said anti-reflecting coating layer is totally removed and said spacer is exposed; forming a second salicide on said conductive layer; removing said spacer; forming a halo and a source drain extension in said substrate, wherein said halo and said source drain extension is located between said gate and said source/drain; and forming a third dielectric layer on said second dielectric layer, wherein said third dielectric layer totally covers said gate.
Claim 2
Independent Claim
217 words
A method for manufacturing a metal oxide semiconductor field effect transistor, said method comprising steps of: providing a substrate; forming an isolation in said substrate; forming a well in said substrate, wherein said well is enclosed by said isolation; forming a first dielectric layer on said substrate; forming a conductive layer on said first dielectric layer; forming an anti-reflection coating layer on said conductive layer; removing portions of said anti-reflection coating layer, said conductive layer and said first dielectric layer to form a gate; forming a source and a drain in said substrate around said gate; forming a spacer on a sidewall of said gate; annealing said source and said drain; forming a first salicide on said source and said drain; forming a second dielectric layer on said substrate, wherein said second dielectric layer totally covers said gate and said spacer; planarizing said second dielectric layer, wherein said anti-reflecting coating layer is totally removed and said spacer is exposed; forming a second salicide on said conductive layer; removing said spacer; forming a halo and a source drain extension in said substrate, wherein said halo and said source drain extension is located between said gate and said source/drain; and forming a third dielectric layer on said second dielectric layer, wherein said third dielectric layer totally covers said gate.
Claim 3
Dependent Claim
14 words
The method according to claim 1 , wherein said isolation comprises shallow junction isolation.
Claim 4
Dependent Claim
16 words
The method according to claim 1 , wherein said first dielectric layer comprises an oxide layer.
Claim 5
Dependent Claim
15 words
The method according to claim 1 , wherein said conductive layer comprises a polysilicon layer.
Claim 6
Dependent Claim
15 words
The method according to claim 1 , wherein said conductive layer comprises a metal layer.
Claim 7
Dependent Claim
17 words
The method according to claim 1 , wherein said anti-reflection coating layer comprises a silicon oxynitride layer.
Claim 8
Dependent Claim
37 words
The method according to claim 1 , wherein the process of removing portions of said antireflection-coating layer, said conductive layer, and said first dielectric layer to form said gate comprises a photolithography process and an etching process.
Claim 9
Dependent Claim
21 words
The method according to claim 1 , wherein the thickness of said shallow junction is about 200 angstroms to 500 angstroms.
Claim 10
Dependent Claim
16 words
The method according to claim 1 , wherein the material of said spacer comprises silicon nitride.
Claim 11
Dependent Claim
17 words
The method according to claim 1 , wherein the material of said first salicide comprises titanium silicide.
Claim 12
Dependent Claim
22 words
The method according to claim 1 , wherein the process of planarizing said second dielectric layer comprises a chemical mechanical polishing process.
Claim 13
Dependent Claim
25 words
The method according to claim 1 , whereby a portion of said conductive layer is removed by said process of planarizing said second dielectric layer.
Claim 14
Dependent Claim
17 words
The method according to claim 1 , wherein the material of said second salicide comprises cobalt silicide.
Claim 15
Dependent Claim
19 words
The method according to claim 1 , wherein the process of removing said spacer comprises a wet etching process.
Claim 16
Dependent Claim
19 words
The method according to claim 14 , wherein an etching solution of said wet etching process comprises sulphuric acid.
Claim 17
Dependent Claim
25 words
The method according to claim 1 , wherein the conductivity type of said halo is opposite to the conductivity type of said source drain extension.
Claim 18
Dependent Claim
17 words
The method according to claim 1 , wherein said halo is located behind said source drain extension.
Claim 19
Independent Claim
209 words
A method for manufacturing a metal oxide semiconductor field effect transistor, said method comprising steps of: providing a substrate; forming an isolation in said substrate; forming a well in said substrate, wherein said well is enclosed by said isolation; forming a first dielectric layer on said substrate; forming a metal layer on said first dielectric layer; forming an anti-reflection coating layer on said metal layer; removing portions of said anti-reflection coating layer, said metal layer and said first dielectric layer to form a gate; forming a source and a drain in said substrate around said gate; forming a spacer on a sidewall of said gate; annealing said source and said drain; forming a first salicide on said source and said drain; forming a second dielectric layer on said substrate, wherein said second dielectric layer totally covers said gate and said spacer; planarizing said second dielectric layer, wherein said anti-reflecting coating layer is totally removed and said spacer is exposed; removing said spacer; forming a halo and a source drain extension in said substrate, wherein said halo and said source drain extension is located between said gate and said source/drain; and forming a third dielectric layer on said second dielectric layer, wherein said third dielectric layer totally covers said gate.
Claim 20
Independent Claim
209 words
A method for manufacturing a metal oxide semiconductor field effect transistor, said method comprising steps of: providing a substrate; forming an isolation in said substrate; forming a well in said substrate, wherein said well is enclosed by said isolation; forming a first dielectric layer on said substrate; forming a metal layer on said first dielectric layer; forming an anti-reflection coating layer on said metal layer; removing portions of said anti-reflection coating layer, said metal layer and said first dielectric layer to form a gate; forming a source and a drain in said substrate around said gate; forming a spacer on a sidewall of said gate; annealing said source and said drain; forming a first salicide on said source and said drain; forming a second dielectric layer on said substrate, wherein said second dielectric layer totally covers said gate and said spacer; planarizing said second dielectric layer, wherein said anti-reflecting coating layer is totally removed and said spacer is exposed; removing said spacer; forming a halo and a source drain extension in said substrate, wherein said halo and said source drain extension is located between said gate and said source/drain; and forming a third dielectric layer on said second dielectric layer, wherein said third dielectric layer totally covers said gate.
References Cited (Backward Citations)
US5162884A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-08-13 | 2005-02-12 | 2005-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-13 | 2009-02-12 | 2009-08-14 | $3760.00 | Window Closed / Lapsed |
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