US6266730B1
Expired / Lapsed
US
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High-frequency bus system
Assignee: Rambus Inc
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Filing: 2000-02-18
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Granted: 2001-07-24
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Expires: 2020-02-18
Abstract
Abstract A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
Inventors
- 👤 Donald V. Perino
- 👤 Billy Wayne Garrett, Jr.
- 👤 Haw-Jyh Liaw
- 👤 David Nguyen
- 👤 Srinivas Nimmagadda
- 👤 James A. Gasbarro
- 👤 Richard DeWitt Crisp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:56
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/063; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1684; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4086; G06F13/409; G06F13/42; G06F13/4247; G11C5/02; G11C5/04; H; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0237; H05K1/0246; H05K1/0248; H05K7/00; H05K7/14; H05K7/1438; H05K7/1459; G11C7/00; G11C7/10; G11C7/1048; H05K1/0216; H05K1/023; H05K1/14; H05K2201/00; H05K2201/04; H05K2201/044; H05K2201/09; H05K2201/09209; H05K2201/09218; H05K2201/09263; H05K2201/10; H05K2201/10007; H05K2201/10022; H05K2201/10159; H05K2201/10613; H05K2201/10621; H05K2201/10689
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
59 words
A memory module, comprising: a substrate; a plurality of integrated circuit memory devices mounted on said substrate; first and second edge terminals positioned on said substrate; and a bus positioned on said substrate, said bus being coupled to each of said plurality of integrated circuit memory devices and extending from said first edge terminal to said second edge terminal.
Claim 2
Dependent Claim
59 words
A memory module, comprising: a substrate; a plurality of integrated circuit memory devices mounted on said substrate; first and second edge terminals positioned on said substrate; and a bus positioned on said substrate, said bus being coupled to each of said plurality of integrated circuit memory devices and extending from said first edge terminal to said second edge terminal.
Claim 3
Dependent Claim
28 words
The memory module of claim 1 wherein said first and second edge terminals each includes a plurality of edge fingers to mate with a connector on a motherboard.
Claim 4
Dependent Claim
22 words
The memory module of claim 2 wherein said first and second edge terminals are located on a first edge of said substrate.
Claim 5
Dependent Claim
21 words
The memory module of claim 2 wherein said first and second edge terminals are located on opposite faces of said substrate.
Claim 6
Dependent Claim
25 words
The memory module of claim 4 wherein said first and second edge terminals are located on opposite faces of a single edge of said substrate.
Claim 7
Dependent Claim
25 words
The memory module of claim 1 wherein said bus includes a plurality of signal lines, each of said signal lines have a common electrical length.
Claim 8
Dependent Claim
22 words
The memory module of claim 6 wherein said each signal line of said plurality of signal lines includes a right angle turn.
Claim 9
Dependent Claim
44 words
The memory module of claim 1 wherein said bus includes a signal line with a first segment positioned on a first side of said substrate, a second segment positioned within said substrate, and a third segment positioned on a second side of said substrate.
Claim 10
Dependent Claim
31 words
The memory module of claim 8 wherein said second segment includes dual signal tracks with a loaded impedance corresponding to the loaded impedance of said first segment and said third segment.
Claim 11
Dependent Claim
63 words
A memory system, comprising: a motherboard; a plurality of memory modules positioned on said motherboard, each memory module including a memory module bus and a plurality of memory devices coupled to said memory module bus; and a plurality of motherboard bus segments positioned on said motherboard, said plurality of motherboard bus segments being coupled in electrical series between said plurality of memory modules.
Claim 12
Dependent Claim
63 words
A memory system, comprising: a motherboard; a plurality of memory modules positioned on said motherboard, each memory module including a memory module bus and a plurality of memory devices coupled to said memory module bus; and a plurality of motherboard bus segments positioned on said motherboard, said plurality of motherboard bus segments being coupled in electrical series between said plurality of memory modules.
Claim 13
Dependent Claim
15 words
The memory system of claim 10 further comprising a memory controller positioned on said motherboard.
Claim 14
Dependent Claim
34 words
The memory system of claim 11 wherein said plurality of motherboard bus segments include a first motherboard segment connected between said memory controller and a first memory module of said plurality of memory modules.
Claim 15
Dependent Claim
35 words
The memory system of claim 10 wherein said motherboard includes a first connection site with a socket and a first memory module of said plurality of memory modules includes edge fingers to engage said socket.
Claim 16
Dependent Claim
27 words
The memory system of claim 10 wherein each memory module bus includes a plurality of signal lines, each of said signal lines having a common electrical length.
Claim 17
Dependent Claim
51 words
The memory system of claim 14 wherein each signal line of said plurality of signal lines includes a signal line with a first segment positioned on a first side of a substrate, a second segment positioned within said substrate, and a third segment positioned on a second side of said substrate.
Claim 18
Dependent Claim
31 words
The memory system of claim 15 wherein said second segment includes dual signal tracks with a loaded impedance corresponding to the loaded impedance of said first segment and said third segment.
Claim 19
Dependent Claim
134 words
A memory system, comprising: a motherboard; a memory controller positioned on said motherboard; a first memory module positioned on said motherboard, said first memory module including a first memory module bus and a first plurality of memory devices coupled to said first memory module bus; a first motherboard bus segment positioned on said motherboard and connected between said memory controller and a first end of said first memory module bus; a second memory module positioned on said motherboard, said second memory module including a second memory module bus and a second plurality of memory devices coupled to said second memory module bus; and a second motherboard bus segment positioned on said motherboard and connected between a second end of said first memory module bus and a first end of said second memory module bus.
Claim 20
Dependent Claim
134 words
A memory system, comprising: a motherboard; a memory controller positioned on said motherboard; a first memory module positioned on said motherboard, said first memory module including a first memory module bus and a first plurality of memory devices coupled to said first memory module bus; a first motherboard bus segment positioned on said motherboard and connected between said memory controller and a first end of said first memory module bus; a second memory module positioned on said motherboard, said second memory module including a second memory module bus and a second plurality of memory devices coupled to said second memory module bus; and a second motherboard bus segment positioned on said motherboard and connected between a second end of said first memory module bus and a first end of said second memory module bus.
Claim 21
Dependent Claim
29 words
The memory system of claim 17 wherein said motherboard includes a first connection site with a socket and said first memory module includes edge fingers to engage said socket.
Claim 22
Dependent Claim
28 words
The memory system of claim 17 wherein said first memory module bus includes a plurality of signal lines, each of said signal lines having a common electrical length.
Claim 23
Dependent Claim
51 words
The memory system of claim 19 wherein each signal line of said plurality of signal lines includes a signal line with a first segment positioned on a first side of a substrate, a second segment positioned within said substrate, and a third segment positioned on a second side of said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-23 | 2005-01-22 | 2005-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-23 | 2009-01-22 | 2009-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-23 | 2013-01-22 | 2013-07-24 | $7700.00 | Window Closed / Lapsed |