Patent US6327387B1 successfully refreshed from Google Patents.
Patent US6263483B1 successfully refreshed from Google Patents.
US6263483B1
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Method of accessing the generic netlist created by synopsys design compilier
Assignee: Bell Semiconductor LLC
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Filing: 1998-02-20
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Granted: 2001-07-17
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Expires: 2018-02-20
Abstract
Abstract A method of translating an integrated circuit chip (IC) design as represented by RTL code to generic netlist using a logic synthesis tool comprising the steps of parsing the RTL code using analyze command of the logic synthesis tool, building the generic netlist using evaluate command of the logic synthesis tool, and recording the generic netlist to a dump file outside the logic synthesis tool. The dump file comprises characteristics of each input ports of current design, characteristics of each output ports of the current design, and characteristics of each cells of the current design.
Inventors
- 👤 Guy Dupenloup
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:36
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
69 words
A method of translating an integrated circuit chip (IC) design as represented by RTL code into an accessible generic netlist using a logic synthesis tool, said method comprising the steps of: parsing the RTL code using the logic synthesis tool; building the generic netlist using the logic synthesis tool; and causing the logic synthesis tool to write the generic netlist to a dump file outside the logic synthesis tool.
Claim 2
Independent Claim
69 words
A method of translating an integrated circuit chip (IC) design as represented by RTL code into an accessible generic netlist using a logic synthesis tool, said method comprising the steps of: parsing the RTL code using the logic synthesis tool; building the generic netlist using the logic synthesis tool; and causing the logic synthesis tool to write the generic netlist to a dump file outside the logic synthesis tool.
Claim 3
Dependent Claim
35 words
A method according to claim 1 wherein said dump file comprises: characteristics of input ports of a current design; characteristics of output ports of the current design; and characteristics of cells of the current design.
Claim 4
Dependent Claim
38 words
A method according to claim 1 wherein the parsing step is performed by executing an analyze command of the logic synthesis tool and the building step is performed by executing an evaluate command of the logic synthesis tool.
Claim 5
Dependent Claim
61 words
A method according to claim 1 wherein said step of writing the generic netlist to a dump file comprises the steps of: identifying all input ports of the design; determining which nets are connected to each of said identified input ports; and writing, to said dump file, port name, port direction, and connected net for each of said identified input ports.
Claim 6
Dependent Claim
61 words
A method according to claim 1 wherein said step of writing the generic netlist to a dump file comprises the steps of: identifying all output ports of the design; determining which nets are connected to each of said identified output ports; and writing, to said dump file, port name, port direction, and connected net for each of said identified output ports.
Claim 7
Dependent Claim
59 words
A method according to claim 1 wherein said step of writing the generic netlist to a dump file comprises the steps of: identifying all cells of the design; searching for hierarchical attributes of each of said identified cell; identifying pins of each of said identified cells; and writing, to said dump file, each pin, pin direction, and connected net.
Claim 8
Dependent Claim
19 words
A method according to claim 1 wherein the generic netlist is written to the dump file in ASCII format.
Claim 9
Dependent Claim
27 words
A method according to claim 1 wherein the generic netlist is caused to be written to the dump file using shell commands of the logic synthesis tool.
Claim 10
Dependent Claim
28 words
A method according to claim 8 wherein object names are stored in associative arrays in order to avoid calling shell commands to query the same information plural times.
Claim 11
Independent Claim
83 words
A method of extracting a generic netlist from a logic synthesis tool, said method comprising the steps of: extracting hardware characteristics of each input port of a current design using a logic synthesis tool; extracting hardware characteristics of each output port of the current design using the logic synthesis tool; extracting hardware characteristics of each cell of the current design using the logic synthesis tool; and creating a dump file, outside the logic synthesis tool, into which said extracted hardware characteristics are written.
Claim 12
Independent Claim
83 words
A method of extracting a generic netlist from a logic synthesis tool, said method comprising the steps of: extracting hardware characteristics of each input port of a current design using a logic synthesis tool; extracting hardware characteristics of each output port of the current design using the logic synthesis tool; extracting hardware characteristics of each cell of the current design using the logic synthesis tool; and creating a dump file, outside the logic synthesis tool, into which said extracted hardware characteristics are written.
Claim 13
Independent Claim
143 words
A method of extracting a generic netlist from a logic synthesis tool into a dump file outside the logic synthesis tool, said method comprising the steps of: identifying all ports in said generic netlist and a directional attribute of each of said identified ports; identifying all cells in said generic netlist, as well as a hierarchical attribute and a reference name of each of said identified cells; identifying all cell pins in said generic netlist and a directional attribute of each of said identified cell pins; identifying all nets in said generic netlist and pins of each of said identified nets; and writing to the dump file, outside the logic synthesis tool, a list of said identified ports and their attributes, said identified cells and their attributes, said cell pins and their attributes, and said nets and pins of each of said nets.
Claim 14
Independent Claim
143 words
A method of extracting a generic netlist from a logic synthesis tool into a dump file outside the logic synthesis tool, said method comprising the steps of: identifying all ports in said generic netlist and a directional attribute of each of said identified ports; identifying all cells in said generic netlist, as well as a hierarchical attribute and a reference name of each of said identified cells; identifying all cell pins in said generic netlist and a directional attribute of each of said identified cell pins; identifying all nets in said generic netlist and pins of each of said identified nets; and writing to the dump file, outside the logic synthesis tool, a list of said identified ports and their attributes, said identified cells and their attributes, said cell pins and their attributes, and said nets and pins of each of said nets.
Claim 15
Independent Claim
79 words
An apparatus for translating an integrated circuit chip (IC) design as represented by RTL code into an accessible generic netlist using a logic synthesis tool, comprising: a processor; memory connected to said processor; said memory having instructions for said processor to: parse the RTL code using the logic synthesis tool; build the generic netlist using the logic synthesis tool; and cause the logic synthesis tool to write the generic netlist to a dump file outside the logic synthesis tool.
Claim 16
Independent Claim
79 words
An apparatus for translating an integrated circuit chip (IC) design as represented by RTL code into an accessible generic netlist using a logic synthesis tool, comprising: a processor; memory connected to said processor; said memory having instructions for said processor to: parse the RTL code using the logic synthesis tool; build the generic netlist using the logic synthesis tool; and cause the logic synthesis tool to write the generic netlist to a dump file outside the logic synthesis tool.
Claim 17
Independent Claim
70 words
An apparatus for translating an integrated circuit chip (IC) design as represented by RTL code into an accessible generic netlist using a logic synthesis tool, comprising: means for parsing the RTL code using the logic synthesis tool; means for building the generic netlist using the logic synthesis tool; and means for causing the logic synthesis tool to write the generic netlist to a dump file outside the logic synthesis tool.
Claim 18
Independent Claim
70 words
An apparatus for translating an integrated circuit chip (IC) design as represented by RTL code into an accessible generic netlist using a logic synthesis tool, comprising: means for parsing the RTL code using the logic synthesis tool; means for building the generic netlist using the logic synthesis tool; and means for causing the logic synthesis tool to write the generic netlist to a dump file outside the logic synthesis tool.
Claim 19
Dependent Claim
37 words
The apparatus according to claim 13 wherein said dump file comprises: characteristics of each input port of current design; characteristics of each output port of the current design; and characteristics of each cell of the current design.
Claim 20
Dependent Claim
23 words
The apparatus according to claim 13 further comprising means for reading mapped netlists which are combined with the analyzed and evaluated IC design.
Claim 21
Dependent Claim
63 words
The apparatus according to claim 13 wherein said means for writing the generic netlist to a dump file comprises: means for identifying all input ports of the design; means for determining which nets are connected to each of said identified input ports; means for writing, to said dump file, port name, port direction, and connected net for each of said identified input ports.
Claim 22
Dependent Claim
64 words
The apparatus according to claim 13 wherein said means for writing the generic netlist to a dump file comprises: means for identifying all output ports of the design; means for determining which nets are connected to each of said identified output ports; and means for writing, to said dump file, port name, port direction, and connected net for each of said identified output ports.
Claim 23
Dependent Claim
64 words
An apparatus according to claim 13 wherein said means for writing the generic netlist to a dump file comprises: means for identifying all cells of the design; means for searching for hierarchical attributes of each of said identified cell; means for identifying pins of each of said identified cells; and means for writing, to said dump file, each pin, pin direction, and connected net.
Claim 24
Independent Claim
123 words
A method of extracting a generic netlist from a logic synthesis tool, said method comprising the steps of: generating a generic netlist from a current design using a logic synthesis tool; extracting hardware characteristics of each input sort of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; extracting hardware characteristics of each output port of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; extracting hardware characteristics of each cell of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; and creating a dump file, outside the logic synthesis tool, into which said extracted hardware characteristics are written.
Claim 25
Independent Claim
123 words
A method of extracting a generic netlist from a logic synthesis tool, said method comprising the steps of: generating a generic netlist from a current design using a logic synthesis tool; extracting hardware characteristics of each input sort of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; extracting hardware characteristics of each output port of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; extracting hardware characteristics of each cell of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; and creating a dump file, outside the logic synthesis tool, into which said extracted hardware characteristics are written.
Claim 26
Dependent Claim
148 words
A computer-readable medium storing computer-executable process steps for extracting a generic netlist from a logic synthesis tool into a dump file outside the logic synthesis tool, said process steps comprising steps to: identify all ports in said generic netlist and a directional attribute of each of said identified ports; identify all cells in said generic netlist as well as a hierarchical attribute and a reference name of each of said identified cells; identify all cell pins in said generic netlist and a directional attribute of each of said identified cell pins; identify all nets in said generic netlist and pins of each of said identified nets; and write to the dump file, outside the logic synthesis tool, a list of said identified ports and their attributes, said identified cells and their attributes, said cell pins and their attributes, and said nets and pins of each of said nets.
Claim 27
Dependent Claim
148 words
A computer-readable medium storing computer-executable process steps for extracting a generic netlist from a logic synthesis tool into a dump file outside the logic synthesis tool, said process steps comprising steps to: identify all ports in said generic netlist and a directional attribute of each of said identified ports; identify all cells in said generic netlist as well as a hierarchical attribute and a reference name of each of said identified cells; identify all cell pins in said generic netlist and a directional attribute of each of said identified cell pins; identify all nets in said generic netlist and pins of each of said identified nets; and write to the dump file, outside the logic synthesis tool, a list of said identified ports and their attributes, said identified cells and their attributes, said cell pins and their attributes, and said nets and pins of each of said nets.
Claim 28
Dependent Claim
73 words
A computer storage medium containing instructions for translating an integrated circuit chip (IC) design as represented by RTL code into an accessible generic netlist using a logic synthesis tool, said instructions comprising the steps of: parsing the RTL code using the logic synthesis tool; building the generic netlist using the logic synthesis tool; and causing the logic synthesis tool to write the generic netlist to a dump file outside the logic synthesis tool.
Claim 29
Dependent Claim
73 words
A computer storage medium containing instructions for translating an integrated circuit chip (IC) design as represented by RTL code into an accessible generic netlist using a logic synthesis tool, said instructions comprising the steps of: parsing the RTL code using the logic synthesis tool; building the generic netlist using the logic synthesis tool; and causing the logic synthesis tool to write the generic netlist to a dump file outside the logic synthesis tool.
Claim 30
Dependent Claim
36 words
A computer storage medium of claim 21 wherein said computer storage medium is selected from a group consisting of magnetic device, optical device, magneto-optical device, floppy diskette, CD-ROM, magnetic tape, computer hard drive, and memory card.
Claim 31
Dependent Claim
21 words
A computer storage medium according to claim 21 wherein the generic netlist is written to the dump file in ASCII format.
Claim 32
Dependent Claim
29 words
A computer storage medium according to claim 21 wherein the generic netlist is caused to be written to the dump file using shell commands of the logic synthesis tool.
Claim 33
Dependent Claim
30 words
A computer storage medium according to claim 24 wherein object names are stored in associative arrays in order to avoid calling shell commands to query the same information plural times.
Claim 34
Dependent Claim
88 words
A computer-readable medium storing computer-executable process steps for extracting a generic netlist from a logic synthesis tool, said process steps comprising steps to: extract hardware characteristics of each input port of a current design using a logic synthesis tool; extract hardware characteristics of each output port of the current design using the logic synthesis tool; extract hardware characteristics of each cell of the current design using the logic synthesis tool; and create a dump file, outside the logic synthesis tool, into which said extracted hardware characteristics are written.
Claim 35
Dependent Claim
88 words
A computer-readable medium storing computer-executable process steps for extracting a generic netlist from a logic synthesis tool, said process steps comprising steps to: extract hardware characteristics of each input port of a current design using a logic synthesis tool; extract hardware characteristics of each output port of the current design using the logic synthesis tool; extract hardware characteristics of each cell of the current design using the logic synthesis tool; and create a dump file, outside the logic synthesis tool, into which said extracted hardware characteristics are written.
Claim 36
Dependent Claim
128 words
A computer-readable medium storing computer-executable process steps for extracting a generic netlist from a logic synthesis tool, said process steps comprising steps to: generate a generic netlist from a current design using a logic synthesis tool; extract hardware characteristics of each input port of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; extract hardware characteristics of each output port of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; extract hardware characteristics of each cell of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; and create a dump file, outside the logic synthesis tool, into which said extracted hardware characteristics are written.
Claim 37
Dependent Claim
128 words
A computer-readable medium storing computer-executable process steps for extracting a generic netlist from a logic synthesis tool, said process steps comprising steps to: generate a generic netlist from a current design using a logic synthesis tool; extract hardware characteristics of each input port of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; extract hardware characteristics of each output port of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; extract hardware characteristics of each cell of the current design by using shell commands of the logic synthesis tool to analyze the generic netlist; and create a dump file, outside the logic synthesis tool, into which said extracted hardware characteristics are written.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-16 | 2005-01-15 | 2005-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-16 | 2009-01-15 | 2009-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-16 | 2013-01-15 | 2013-07-17 | $7700.00 | Window Closed / Lapsed |