Equipotential sense methods for resistive cross point memory cell arrays

Claim 3

The method of claim 1 , wherein a current source is used to supply a current to the selected bit line and a voltage follower is used to detect the first potential and apply the third potential to the subset of unselected lines.

Claim 4

The method of claim 2 , wherein the current source is a charge pump that provides a constant current to the selected bit line; and wherein the resistance state of the selected memory cell is determined by comparing a threshold to a potential at a junction between the current source and the selected memory cell, the comparison indicating whether the selected memory cell has a high or low resistance state.

Claim 5

The method of claim 1 , wherein a current sense amplifier is connected between the selected bit line and a virtual ground; and wherein the third potential is applied to the subset of unselected lines by connecting said subset to the virtual ground.

Claim 6

The method of claim 4 , wherein the sense amplifier includes an active amplifier; and wherein the resistance state is determined by using the active amplifier to amplify a signal on the selected bit line, and comparing the amplified signal to a reference voltage, the comparison indicating whether the selected memory cell has a high or low resistance state.

Claim 7

The method of claim 1 , wherein a decaying first potential is applied to the selected bit line; and wherein a decay time is observed to determine the resistive state of the selected memory cell.

Claim 8

The method of claim 6 , further comprising the step of using a charge amplifier to regulate the voltage on the selected bit line while the decaying first potential being is applied to the selected bit line.

Claim 9

The method of claim 6 , wherein the resistance is determined by integrating a current flowing through the selected memory cell, and determining whether the memory cell has a high or low resistance according to integration time of the current.

Claim 10

The method of claim 8 , further comprising the step of allowing a steady state current to flow through the selected memory cell before the current integration is performed.

Claim 11

The method of claim 1 , wherein the third potential is applied to the unselected bit lines in the neighborhood of the selected bit line.

Claim 12

Apparatus for reading a selected memory cell in a resistive cross point array of memory cells, a plurality of word lines crossing rows of the memory cells, a plurality of bit lines crossing columns of the memory cells, the apparatus comprising: means for applying a first potential to a selected bit line crossing the selected memory cell and a second potential to a selected word line crossing the selected memory cell; means for applying a third potential to a subset of unselected word and bit lines, the third potential being equal to the first potential; and means for determining the resistance state of the selected memory cell while the potentials are being applied to the selected lines and the subset of unselected lines.

Claim 13

Apparatus for reading a selected memory cell in a resistive cross point array of memory cells, a plurality of word lines crossing rows of the memory cells, a plurality of bit lines crossing columns of the memory cells, the apparatus comprising: means for applying a first potential to a selected bit line crossing the selected memory cell and a second potential to a selected word line crossing the selected memory cell; means for applying a third potential to a subset of unselected word and bit lines, the third potential being equal to the first potential; and means for determining the resistance state of the selected memory cell while the potentials are being applied to the selected lines and the subset of unselected lines.

Claim 14

A data storage device comprising: a resistive cross point array of memory cells; a plurality of word lines extending along rows of the array; a plurality of bit lines extending along columns of the array; and a circuit for sensing resistance states of selected memory cells during read operations on the selected memory cells, the circuit applying a first potential to selected bit lines, a second potential to selected word lines and a third potential to subsets of unselected word and bit lines, the third potential being equal to the first potential.

Claim 15

A data storage device comprising: a resistive cross point array of memory cells; a plurality of word lines extending along rows of the array; a plurality of bit lines extending along columns of the array; and a circuit for sensing resistance states of selected memory cells during read operations on the selected memory cells, the circuit applying a first potential to selected bit lines, a second potential to selected word lines and a third potential to subsets of unselected word and bit lines, the third potential being equal to the first potential.

Claim 16

The device of claim 12 , wherein the circuit includes a current source, steering switches for coupling the current source to selected bit lines during read operations, and a voltage follower for detecting the first potential and applying the third potential to the subset of unselected lines during read operations.

Claim 17

The device of claim 13 , wherein the current source includes a charge pump; and wherein the circuit further includes a comparator for comparing a reference voltage to a potential at a junction between the current source and the selected bit line during a read operation.

Claim 18

The device of claim 12 , wherein the circuit applies a sense voltage source to the selected word line during a read operation; and wherein the circuit includes a current sense amplifier and steering switches for connecting the current sense amplifier between the selected bit line and a virtual ground during a read operation, whereby the first potential is applied to the selected bit line; and wherein the steering switches connect the subset of unselected lines to the virtual ground during the read operation.

Claim 19

The device of claim 15 , wherein the sense amplifier includes an active amplifier; and wherein the circuit further includes a comparator for comparing an output of the active amplifier to a reference voltage, an output of the comparator indicating whether the selected memory cell has a high or low resistance state.

Claim 20

The device of claim 12 , wherein the circuit includes a capacitor for providing a decaying first potential to the selected bit line during read operations.

Claim 21

The device of claim 17 , wherein the circuit further includes a charge amplifier for regulating the first potential on the selected bit line while the capacitor is applying the first potential to the selected bit line.

Claim 22

The device of claim 17 , wherein the circuit further includes a sense amplifier for integrating a current flowing through the selected memory cell and determining whether the selected memory cell has a high or low resistance according to decay time of capacitor voltage.

Claim 23

The device of claim 19 , wherein the memory cells are MRAM cells.

Claim 24

Apparatus for reading a selected memory cell in a resistive cross point array of memory cells, the selected memory cell being at a cross point of first and second selected traces, the apparatus comprising: means for applying a first potential to the first trace and a second potential to the second trace; means for applying a third potential to a subset of traces not crossing the selected memory cell, the third potential being equal to the first potential; and means for determining the resistance state of the selected memory cell while the potentials are being applied to the selected traces and the subset of unselected traces.

Claim 25

Apparatus for reading a selected memory cell in a resistive cross point array of memory cells, the selected memory cell being at a cross point of first and second selected traces, the apparatus comprising: means for applying a first potential to the first trace and a second potential to the second trace; means for applying a third potential to a subset of traces not crossing the selected memory cell, the third potential being equal to the first potential; and means for determining the resistance state of the selected memory cell while the potentials are being applied to the selected traces and the subset of unselected traces.

Claim 26

A data storage device comprising: a resistive cross point array of memory cells; a plurality of first traces lines extending along the array in a first direction; a plurality of second traces extending along the array in a second direction, each memory cell being at a cross point of one of the first traces and one of the second traces; and a circuit for sensing resistance states of selected memory cells during read operations on the selected memory cells, the circuit applying a first potential to the first traces crossing the selected memory cells, a second potential to the second traces crossing the selected memory cells, and a third potential to subsets of traces not crossing the selected memory cells, the third potential being equal to the first potential.

Claim 27

A data storage device comprising: a resistive cross point array of memory cells; a plurality of first traces lines extending along the array in a first direction; a plurality of second traces extending along the array in a second direction, each memory cell being at a cross point of one of the first traces and one of the second traces; and a circuit for sensing resistance states of selected memory cells during read operations on the selected memory cells, the circuit applying a first potential to the first traces crossing the selected memory cells, a second potential to the second traces crossing the selected memory cells, and a third potential to subsets of traces not crossing the selected memory cells, the third potential being equal to the first potential.

Claim 28

The device of claim 22 , wherein the circuit includes a current source and a voltage follower for detecting the first potential and applying the third potential to the subset of unselected traces during read operations.

Claim 29

The device of claim 23 , wherein the current source includes a charge pump; and wherein the circuit further includes a comparator for comparing a reference voltage to a potential at a junction between the current source and a selected trace during a read operation.

Claim 30

The device of claim 22 , wherein the circuit includes a current sense amplifier connected to a virtual ground during a read operation; and wherein the circuit applies a sense voltage source to one of the selected first and second traces during a read operation and connects the subset of unselected traces to the virtual ground during the read operation.

Claim 31

The device of claim 25 , wherein the sense amplifier includes an active amplifier; and wherein the circuit further includes a comparator for comparing an output of the active amplifier to a reference voltage, an output of the comparator indicating whether the selected memory cell has a high or low resistance state.

Claim 32

The device of claim 22 , wherein the circuit includes a capacitor for providing a decaying first potential to selected traces during read operations.

Claim 33

The device of claim 27 , wherein the circuit further includes a charge amplifier for regulating the first potential on the selected traces while the capacitor is applying the first potential to the selected traces.

Claim 34

The device of claim 27 , wherein the circuit further includes a sense amplifier for integrating a current flowing through the selected memory cells and determining whether the selected memory cells have a high or low resistance according to decay time of capacitor voltage.

Claim 35

The device of claim 22 , wherein the memory cells are magnetic memory cells.