Serial-parallel converter circuit

Claim 2

A serial-parallel converter comprising: a plurality of data extraction units for sequentially extracting different bit values of serial data, which are sequentially inputted, for individually holding said different bit values for a time period corresponding to the same number of cycles of a clock signal as the number of said data extraction units until said plurality of data extraction units extract next bit values of said serial data; a delay unit connected to said plurality of data extraction units for receiving data signals from said plurality of data extraction units and delaying said data signals to generate delay signals which synchronize with each other; and a parallel register connected to said delay unit for receiving said delay signals from said delay unit for latching said delay signals to output said delay signals simultaneously as parallel data.

Claim 3

The serial-parallel converter as claimed in claim 1 , wherein each of said plurality of data extraction units comprises: a flip-flop circuit operable in synchronizing with said clock signal; and a selector connected to said flip-flop circuit for receiving an output value from said flip-flop circuit so that said selector selects one of said output value from said flip-flop circuit and said bit value of said serial data to render selected one inputted into said flip-flop circuit.

Claim 4

The serial-parallel converter as claimed in claim 2 , wherein if said selector selects said bit value of said serial data, then said selector selects said output value from said flip-flop circuit after said output value from said flip-flop circuit has been changed to said bit value.

Claim 5

The serial-parallel converter as claimed in claim 1 , wherein said delay unit delays said data signals in synchronizing with mostly-delayed one of said data signals.

Claim 6

The serial-parallel converter as claimed in claim 1 , wherein said delay unit comprises the same number of delay blocks as the number of said plurality of data extraction units, so that said delay blocks are individually connected to said plurality of data extraction units.

Claim 7

The serial-parallel converter as claimed in claim 1 , further comprising a trigger generator connected to said plurality of data extraction units for supplying individual latch signals, which synchronizing with said clock signal, to said plurality of data extraction units, so that, on the basis of said individual latch signals as triggers, said plurality of data extraction units do sequentially extract different bit values of said serial data having sequentially inputted to said plurality of data extraction units.

Claim 8

The serial-parallel converter as claimed in claim 6 , wherein said trigger generator is connected to said parallel resistor for supplying a load signal to said parallel resistor, so that said parallel resistor fetches said delay signals from said delay unit on the basis of said load signal.

Claim 9

The serial-parallel converter as claimed in claim 7 , wherein said trigger generator comprises: a counter for counting said clock signal to generate binary digits and for generating timings to fetch said serial data; and a decoder connected to said counter for receiving said binary digits from said counter to generate said latch signals and said load signal.

Claim 10

The serial-parallel converter as claimed in claim 7 , wherein said trigger generator comprises a shift resistor.

Claim 11

A serial-parallel converter comprising: plural data extraction units for sequentially extracting bit values of serial data sequentially input thereto and for individually holding the bit values for a time period corresponding to a number of cycles of a clock signal equal to a number of said plural data extraction units, each of said plural data extraction units comprising a flip-flop synchronously operating with the clock signal; a delay unit connected to said plural data extraction units for receiving data signals from said plural data extraction units and delaying the data signals to generate delay signals that are synchronized with each other; a parallel register connected to said delay unit and receiving the delay signals therefrom for latching the delay signals to output the delay signals simultaneously as parallel data; and a trigger generator connected to each of said plural data extraction units for providing individual latch signals synchronously with the clock signal to said plural data extraction units, said trigger generator also being connected to said parallel register and providing a load signal thereto so that said parallel register fetches the delay signals on the basis of the load signal, said trigger generator comprising, a counter for counting the clock signal to generate binary digits and for generating timing signals for fetching the serial data, and a decoder connected to said counter and receiving the binary digits to generate the latch signals and the load signal.

Claim 12

A serial-parallel converter comprising: plural data extraction units for sequentially extracting bit values of serial data sequentially input thereto and for individually holding the bit values for a time period corresponding to a number of cycles of a clock signal equal to a number of said plural data extraction units, each of said plural data extraction units comprising a flip-flop synchronously operating with the clock signal; a delay unit connected to said plural data extraction units for receiving data signals from said plural data extraction units and delaying the data signals to generate delay signals that are synchronized with each other; a parallel register connected to said delay unit and receiving the delay signals therefrom for latching the delay signals to output the delay signals simultaneously as parallel data; and a trigger generator connected to each of said plural data extraction units for providing individual latch signals synchronously with the clock signal to said plural data extraction units, said trigger generator also being connected to said parallel register and providing a load signal thereto so that said parallel register fetches the delay signals on the basis of the load signal, said trigger generator comprising, a counter for counting the clock signal to generate binary digits and for generating timing signals for fetching the serial data, and a decoder connected to said counter and receiving the binary digits to generate the latch signals and the load signal.

Claim 13

A serial-parallel converter comprising: plural data extraction units for sequentially extracting bit values of serial data sequentially input thereto and for individually holding the bit values for a time period corresponding to a number of cycles of a clock signal equal to a number of said plural data extraction units; a delay unit connected to said plural data extraction units for receiving data signals from said plural data extraction units and delaying the data signals to generate delay signals that are synchronized with each other; a parallel register connected to said delay unit and receiving the delay signals therefrom for latching the delay signals to output the delay signals simultaneously as parallel data; and a trigger generator connected to each of said plural data extraction units for providing individual latch signals synchronously with the clock signal to said plural data extraction units, said trigger generator also being connected to said parallel register and providing a load signal thereto so that said parallel register fetches the delay signals on the basis of the load signal, said trigger generator comprising a shift register.

Claim 14

A serial-parallel converter comprising: plural data extraction units for sequentially extracting bit values of serial data sequentially input thereto and for individually holding the bit values for a time period corresponding to a number of cycles of a clock signal equal to a number of said plural data extraction units; a delay unit connected to said plural data extraction units for receiving data signals from said plural data extraction units and delaying the data signals to generate delay signals that are synchronized with each other; a parallel register connected to said delay unit and receiving the delay signals therefrom for latching the delay signals to output the delay signals simultaneously as parallel data; and a trigger generator connected to each of said plural data extraction units for providing individual latch signals synchronously with the clock signal to said plural data extraction units, said trigger generator also being connected to said parallel register and providing a load signal thereto so that said parallel register fetches the delay signals on the basis of the load signal, said trigger generator comprising a shift register.