Serial data interface circuit dealing with a plurality of receiving modes

Claim 2

A serial interface circuit comprising: an input terminal supplied with serial data, a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal, selector means for selecting said input terminal in a first mode and an output of said first shift register in a second mode, a second shift register fetching and shifting data at an output of said selector means in synchronism with said clock signal, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively, a set of first output terminals, a set of second output terminals, first transferring means for transferring said first and second data to said first and second output terminals in said second mode, and second transferring means for transferring one of said first and second data to one of said first and second output terminals in said first mode.

Claim 3

The circuit as claimed in claim 1, wherein said first transferring means includes a first tristate buffer having a set of input nodes supplied with said first data and a set of output nodes connected to said first output terminals and said second transferring means includes a second tristate buffer having a set of input nodes supplied with said second data and a set of output nodes connected to said second output terminals, both of said first and second tristate buffers being activated in said second mode and one of said first and second tristate buffers being activated in said first mode.

Claim 4

The circuit as claimed in claim 2, wherein said first transferring means further includes a third tristate buffer having a set of input nodes supplied each with a predetermined logic level and a set of output nodes connected to said first output terminals, both of said second and third tristate buffers being activated and said first tristate buffer being deactivated in said first mode.

Claim 5

The circuit as claimed in claim 2, said second transferring means further includes a third tristate buffer having a set of input nodes each supplied with a predetermined logic level and a set of output nodes connected to said second output terminals, both of said first and third tristate buffers being activated and said second tristate buffer being deactivated in said first mode.

Claim 6

A serial interface circuit comprising an input terminal supplied with serial data, a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal, a selector for selecting said input terminal in a first mode and an output of said first shift register in a second mode, a second shift register fetching and shifting data at an output of said selector, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively, a set of first output terminals, a set of second output terminals, first transferring means for transferring said first and second data to said first and second output terminals with reversing bit orders of said first and second data, and second transferring means for transferring one of a said first and second data to one of said first and second output terminals with reversing the bit order of said one of said first and second data.

Claim 7

A serial interface circuit comprising an input terminal supplied with serial data, a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal, a selector for selecting said input terminal in a first mode and an output of said first shift register in a second mode, a second shift register fetching and shifting data at an output of said selector, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively, a set of first output terminals, a set of second output terminals, first transferring means for transferring said first and second data to said first and second output terminals with reversing bit orders of said first and second data, and second transferring means for transferring one of a said first and second data to one of said first and second output terminals with reversing the bit order of said one of said first and second data.

Claim 8

The circuit as claimed claim 5, wherein said first and second transferring means are constructed by including a first tristate buffer having a set of input nodes supplied with said first data with reversing the bit order thereof and a set of output nodes connected to said second output terminals a second tristate buffer having a set of input nodes supplied with said second data with reversing the bit order thereof and a set of output nodes connected to said first output terminals, both of said first and second tristate buffers being activated in said second mode and one of said first and second tristate buffers being activated in said first mode.

Claim 9

A serial interface circuit comprising an input terminal supplied with serial data, a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal, a selector for selecting said input terminal in a first and a second mode and for selecting an output of said first shift register in a third and a fourth mode, a second shift register fetching and shifting a data at an output of said selector, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively, a set of first output terminals, a set of second output terminals, first transferring means for transferring said first and second data to said first and second output terminals without reversing bit orders of said first and second data in said third mode, second transferring means for transferring said first and second data to said first and second output terminals with reversing the bit orders of said first and second data in said fourth mode, third transferring means for transferring one of said first and second data to one of said first and second output terminals without reversing the bit order of said one of said first and second data in said first mode, and fourth transferring means for transferring said one of said first and second data to said one of said first and second output terminals with reversing the bit order of said one of said first and second data in said second mode.

Claim 10

A serial interface circuit comprising an input terminal supplied with serial data, a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal, a selector for selecting said input terminal in a first and a second mode and for selecting an output of said first shift register in a third and a fourth mode, a second shift register fetching and shifting a data at an output of said selector, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively, a set of first output terminals, a set of second output terminals, first transferring means for transferring said first and second data to said first and second output terminals without reversing bit orders of said first and second data in said third mode, second transferring means for transferring said first and second data to said first and second output terminals with reversing the bit orders of said first and second data in said fourth mode, third transferring means for transferring one of said first and second data to one of said first and second output terminals without reversing the bit order of said one of said first and second data in said first mode, and fourth transferring means for transferring said one of said first and second data to said one of said first and second output terminals with reversing the bit order of said one of said first and second data in said second mode.

Claim 11

The circuit as claimed in claim 7, wherein said first to fourth means are constructed by including a first tristate buffer having a set of input nodes supplied with said first data without reversing the bit order of said first data and a set of output nodes connected to said first output terminals, a second tristate buffer having a set of input nodes supplied with said second data with reversing the bit order of said second data and a set of output nodes connected to said second output terminals, a third tristate buffer having a set of input nodes supplied with said second data without reversing the bit order of said second data and a set of output nodes connected to said second output terminals, and a fourth tristate buffer having a set of input nodes supplied with said second data with reversing the bit order of said second data and a set of output nodes connected to said first output terminals, only one of said first and third tristate buffers being activated in said first mode, only one of said second and fourth tristate buffers being activated in said second mode, only said first and third tristate buffers being activated in said third mode, and only said second and fourth tristate buffers being activated in said fourth mode.

Claim 12

The circuit as claimed in claim 7, said first and fourth transferring means are constructed by including a selection circuit having a set of first input nodes supplied with said first and second data without reversing the bit order of said first and second data, a set of second input nodes supplied with said first and second data with reversing the bit order of said first and second data, a set of least significant bit output nodes and a set of most significant bit output nodes, a first tristate buffer having a set of input nodes connected to said least significant bit output nodes and a set of output nodes connected to said first output terminals, and a second tristate buffer having a set of input nodes connected to said most significant bit output nodes and a set of output nodes connected to said second output terminals, said selection circuit selecting said first input nodes in said first and third modes and said second input nodes in said second and fourth modes, both of said first and second tristate buffers being activated in said second and third modes, and one of said first and second tristate buffers being activated in said first and fourth modes.