Patent US6256256B1 successfully refreshed from Google Patents.
US6256256B1
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Dual port random access memories and systems using the same
Assignee: FOOTHILLS IP LLC
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Filing: 1998-08-28
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Granted: 2001-07-03
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Expires: 2018-08-28
Abstract
Abstract Memory 900 includes an array 401 of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines. A first port (PORT1) is utilized for accessing selected ones of the memory cells using the first wordline and the first bitline of corresponding ones of the rows and columns, first port (PORT1) associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses via first processing device 101 using a time base and an access-type required by such first processing device. A second port (PORT2) is utilized for accessing selected ones of the memory cells using the second wordline and the second bitline of corresponding ones of the rows and columns, second port (PORT2) associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a second processing device 1002.
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/406; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C7/00; G11C7/18; G11C8/00; G11C8/12; G11C8/16
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
154 words
A frame buffer memory comprising: an array of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines; a first port for accessing selected ones of said memory cells using said first wordline and said first bitline of corresponding ones of said rows and columns, said first port associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses by a CPU using a time base and access type required by said CPU; and a second port for accessing selected ones of said memory cells using said second wordline and said second bitline of corresponding ones of said rows and columns, said second port associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a display controller using a time base and access type required by said display controller.
Claim 2
Dependent Claim
154 words
A frame buffer memory comprising: an array of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines; a first port for accessing selected ones of said memory cells using said first wordline and said first bitline of corresponding ones of said rows and columns, said first port associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses by a CPU using a time base and access type required by said CPU; and a second port for accessing selected ones of said memory cells using said second wordline and said second bitline of corresponding ones of said rows and columns, said second port associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a display controller using a time base and access type required by said display controller.
Claim 3
Dependent Claim
46 words
The memory of claim 1 wherein said first port is operating in response to a first clock of a first frequency and said second port is operating in response to a second clock of a second frequency, said first frequency being greater than said second frequency.
Claim 4
Dependent Claim
20 words
The memory of claim 1 wherein said first and second ports are operating in response to a single system clock.
Claim 5
Dependent Claim
18 words
The memory of claim 1 wherein said frame buffer comprises a portion of a unified frame buffer-system memory.
Claim 6
Dependent Claim
29 words
The memory of claim 1 wherein timing parameters for said first port are in a first ratio and timing parameters for said second port are in a second ratio.
Claim 7
Dependent Claim
13 words
The memory of claim 1 wherein said control signals comprise /RAS and /CAS.
Claim 8
Dependent Claim
12 words
The memory of claim 1 wherein said memory comprises a synchronous DRAM.
Claim 9
Dependent Claim
16 words
The memory of claim 1 wherein said memory cells comprises 2T−1C dynamic random access memory cells.
Claim 10
Dependent Claim
62 words
A frame buffer comprising: a first port having dedicated address, data and control signal inputs for updating display data within said memory using timing parameters and accesses types optimized for use with a selected processing device; and a second port having dedicated address, data and control signal inputs for supporting simultaneous and asynchronous accesses to said frame buffer by a display controller.
Claim 11
Dependent Claim
62 words
A frame buffer comprising: a first port having dedicated address, data and control signal inputs for updating display data within said memory using timing parameters and accesses types optimized for use with a selected processing device; and a second port having dedicated address, data and control signal inputs for supporting simultaneous and asynchronous accesses to said frame buffer by a display controller.
Claim 12
Dependent Claim
108 words
The frame buffer of claim 9 and further comprising: an array of rows and columns of memory cells, each memory cell including a capacitor and first and second pass transistors, said first pass transistor for coupling said capacitor to a first bitline in response to an active signal on a first wordline and said second pass transistor for coupling said capacitor to a second bitline in response to an active signal on a second wordline, said first port for accessing a selected cell using said first bitline and said first wordline and said second port for accessing a selected cell using said second bitline and said second wordline.
Claim 13
Dependent Claim
14 words
The frame buffer of claim 9 wherein said array comprises a stand-alone frame buffer.
Claim 14
Dependent Claim
19 words
The frame buffer of claim 9 wherein said array comprises an allocable memory space in a unified frame-buffer-system memory.
Claim 15
Dependent Claim
13 words
The frame buffer of claim 9 wherein said processing device comprising a CPU.
Claim 16
Dependent Claim
191 words
A processing system comprising: first core logic operating in accordance with a first clock and a first set of memory access parameters; second core logic operating in accordance with a second clock and a second set of memory access parameters; and a multiport memory comprising: a first port coupled to the first core logic and operating in accordance with the first clock and the first set of access parameters; a second port coupled to the second core logic and operating in accordance with the second clock and the second set of access parameters; and an array of rows and columns of memory cells, each memory cell including a capacitor and first and second pass transistors, the first pass transistor for coupling the capacitor to a first bitline in response to an active signal on a first wordline and the second pass transistor for coupling the capacitor to a second bitline in response to an active signal on a second wordline, the first port accessing a selected cell using the first bitline and the first wordline and the second port accessing a selected cell using the second bitline and the second wordline.
Claim 17
Dependent Claim
191 words
A processing system comprising: first core logic operating in accordance with a first clock and a first set of memory access parameters; second core logic operating in accordance with a second clock and a second set of memory access parameters; and a multiport memory comprising: a first port coupled to the first core logic and operating in accordance with the first clock and the first set of access parameters; a second port coupled to the second core logic and operating in accordance with the second clock and the second set of access parameters; and an array of rows and columns of memory cells, each memory cell including a capacitor and first and second pass transistors, the first pass transistor for coupling the capacitor to a first bitline in response to an active signal on a first wordline and the second pass transistor for coupling the capacitor to a second bitline in response to an active signal on a second wordline, the first port accessing a selected cell using the first bitline and the first wordline and the second port accessing a selected cell using the second bitline and the second wordline.
Claim 18
Dependent Claim
22 words
The system of claim 14 wherein the first processing device comprises a CPU and the second processing device comprises a display controller.
Claim 19
Dependent Claim
39 words
The system of claim 14 wherein the first processing device is operating in response to a first clock of a first frequency and the second processing device is operating in response to a second clock of a second frequency.
Claim 20
Dependent Claim
12 words
The system of claim 16 wherein the first and second frequencies differ.
Claim 21
Dependent Claim
31 words
The system of claim 14 wherein the first set of access parameters are in a first predetermined ratio and the second set of access parameters are in a second predetermined ratio.
Claim 22
Dependent Claim
13 words
The system of claim 18 wherein the first and second predetermined ratios differ.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-02 | 2005-01-01 | 2005-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-02 | 2009-01-01 | 2009-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-02 | 2013-01-01 | 2013-07-03 | $7700.00 | Window Closed / Lapsed |