Redundant decision circuit for semiconductor memory device

Claim 2

A redundant decision circuit, comprising: a switching element connected between a low potential power supply and a node; a switching driver connected to the switching element for driving the switching element; a fuse; a load circuit connected in series with the fuse between a high potential power supply and the node; and a hold circuit, connected to the node, for latching a potential at the node and generating a redundant decision signal.

Claim 3

The circuit of claim 1 , wherein the load circuit generates a voltage drop in accordance with a current flowing in the fuse.

Claim 4

The circuit of claim 1 , wherein the switching element is an N-channel MOS transistor and the load circuit is an N-channel MOS transistor the gate of which is connected to the high potential power supply.

Claim 5

The circuit of claim 1 , wherein the switching element is an N-channel MOS transistor and the load circuit is two series connected N-channel MOS transistors the gates of which are connected to the high potential power supply.

Claim 6

The circuit of claim 1 , wherein the switching element is an N-channel MOS transistor and the load circuit is a resistor.

Claim 7

The circuit of claim 1 , wherein the switching element is an N-channel MOS transistor and the load circuit is a diode.

Claim 8

A semiconductor memory device, comprising: a memory cell array including a normal cell array and a redundant cell array; a redundant decision circuit for generating a redundant decision signal; and a decoder, connected to the redundant decision circuit, for performing a redundant operation to select a normal cell of the normal cell array or a redundant cell of the redundant cell array in accordance with the redundant decision signal, the redundant decision circuit including, a switching element connected between a low potential power supply and a node, a switching driver connected to the switching element for driving the switching element, a fuse, a load circuit connected in series with the fuse between a high potential power supply and the node, and a hold circuit, connected to the node, for latching a potential at the node and generating the redundant decision signal.

Claim 9

A semiconductor memory device, comprising: a memory cell array including a normal cell array and a redundant cell array; a redundant decision circuit for generating a redundant decision signal; and a decoder, connected to the redundant decision circuit, for performing a redundant operation to select a normal cell of the normal cell array or a redundant cell of the redundant cell array in accordance with the redundant decision signal, the redundant decision circuit including, a switching element connected between a low potential power supply and a node, a switching driver connected to the switching element for driving the switching element, a fuse, a load circuit connected in series with the fuse between a high potential power supply and the node, and a hold circuit, connected to the node, for latching a potential at the node and generating the redundant decision signal.