US6256235B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Adjustable driver pre-equalization for memory subsystems
Assignee: Micron Technology Inc
•
Filing: 2000-06-23
•
Granted: 2001-07-03
•
Expires: 2020-06-23
Abstract
Abstract A method and apparatus are disclosed for programmably tailoring the waveform of a data signal applied to a data path of a data bus to compensate for signal distortions to the data signal as it travels over the data path.
Inventors
- 👤 Terry R. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:10
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 118
Claim 1
Independent Claim
60 words
A memory circuit, comprising: at least one signal generator for generating at least one data signal on a data path of a memory bus, said signal generator comprising: a driver circuit for generating an output data signal on a data path; and a circuit for programmably altering a waveform shape of the output data signal generated by said driver circuit.
Claim 2
Dependent Claim
60 words
A memory circuit, comprising: at least one signal generator for generating at least one data signal on a data path of a memory bus, said signal generator comprising: a driver circuit for generating an output data signal on a data path; and a circuit for programmably altering a waveform shape of the output data signal generated by said driver circuit.
Claim 3
Dependent Claim
22 words
A memory circuit as in claim 1 wherein said programmably altering circuit programmably alters the slew rate of said output data signal.
Claim 4
Dependent Claim
26 words
A memory circuit as in claim 1 wherein said programmably altering circuit programmably alters the amplitude of at least a portion of the output data signal.
Claim 5
Dependent Claim
30 words
A memory circuit as in claim 1 wherein said programmably altering circuit programmably alters the slew rate and the amplitude of at least a portion of said output data signal.
Claim 6
Dependent Claim
30 words
A memory circuit as in claim 1 wherein said programmably altering circuit alters the shape of at least one of a rising and falling edge of said output data signal.
Claim 7
Dependent Claim
26 words
A memory circuit as in claim 1 wherein said driver circuit and said programmably altering circuit are provided at a controller for a memory bus system.
Claim 8
Dependent Claim
23 words
A memory circuit as in claim 1 wherein said driver circuit and said programmably altering circuit are provided at a memory storage device.
Claim 9
Dependent Claim
22 words
A memory circuit as in claim 1 wherein said driver circuit and said programmably altering circuit are provided on a memory module.
Claim 10
Dependent Claim
33 words
A memory circuit as in claim 8 wherein said driver circuit and a said programmably altering circuit are respectively provided at each of a plurality of memory storage devices on said memory module.
Claim 11
Dependent Claim
50 words
A memory circuit as in claim 8 wherein a said driver circuit is respectively provided at each of a plurality of memory storage devices on said memory module and said programmably altering circuit is provided on said memory module to commonly control the driver circuits of said memory storage devices.
Claim 12
Dependent Claim
42 words
A memory circuit as in claim 1 , wherein said driver circuit comprises at least one paired pull-up and pull-down elements, at least one of which is controllable, said programmably altering circuit providing at least one control signal to said controllable element.
Claim 13
Dependent Claim
40 words
A memory circuit as in claim 1 wherein said driver circuit comprises at least one paired pull-up and pull-down driving elements and said programmably altering circuit provides control signals to said at least one paired pull-up and pull-down driving elements.
Claim 14
Dependent Claim
60 words
A memory circuit as in claim 1 wherein said driver circuit comprises a plurality of paired pull-up and pull-down driving elements, the outputs of said paired pull-up and pull-down driving elements being commonly connected to said data path, and said programmably altering circuit provides control signals to said paired pull-up and pull-down driving elements in accordance with applied program signals.
Claim 15
Dependent Claim
40 words
A memory circuit as in claim 13 wherein said programmably altering circuit comprises a plurality of programmable circuits each of which respectively controls paired pull-up and pull-down driving elements, each of said programmable circuits being responsive to respective program signals.
Claim 16
Dependent Claim
38 words
A memory circuit as in claim 14 wherein each of said programmable circuits is responsive to a first program signal to control whether a particular programmable circuit is operative to control a respective pair of pull-up-and pull-down elements.
Claim 17
Dependent Claim
48 words
A memory circuit as in claim 15 wherein each of said programmable circuits is responsive to at least one second program signal to control the drive strength of at least one of said pull up and pull down elements of a respective pair of pull-up and pull-down elements.
Claim 18
Dependent Claim
42 words
A memory circuit as in claim 16 wherein each of said programmable circuits is responsive to at least two second program signals to control the drive strength of said pull-up and pull-down elements of a respective pair of pull-up and pull-down elements.
Claim 19
Dependent Claim
39 words
A memory circuit as in claim 17 wherein each of said programmable circuits is responsive to a respective one of said second program signals to control the drive strength of a respective one of said pull-up and pull-down elements.
Claim 20
Dependent Claim
25 words
A memory circuit as in claim 1 further comprising a circuit responsive to programming signals for generating programming signal commands to said programmably altering circuit.
Claim 21
Dependent Claim
38 words
A memory circuit as in claim 19 wherein said programming signal command generating circuit comprises a register for receiving a digital programming command and a circuit portion for generating said programming signal commands based on said register contents.
Claim 22
Dependent Claim
59 words
A memory circuit as in claim 20 wherein said driver circuit comprises a plurality of first driver circuits having a common output on said data path, and said programmably altering circuit comprises a plurality of programmable circuits, each coupled to drive a respective first driver circuit, said circuit portion generating programming signal commands for said plurality of programmable circuits.
Claim 23
Dependent Claim
29 words
A memory circuit as in claim 21 wherein said circuit portion for generating programming signal commands generates respective programming signal commands for each of said plurality of programmable circuits.
Claim 24
Dependent Claim
52 words
A memory circuit as in claim 20 wherein said respective programming signal commands include a first programming signal which determines whether a respective programmable circuit is operative, and at least one second programming signal which causes said respective programmable circuit to determine a drive strength characteristic of a respective first driver circuit.
Claim 25
Dependent Claim
54 words
A memory circuit as in claim 23 , wherein each said first driver circuit includes at least one pull-up element and at least one pull-down element, at least one of said pull-up and pull-down elements being controllable and said respective programming signal commands include commands to control the drive strength of said controllable element.
Claim 26
Dependent Claim
61 words
A memory circuit as in claim 23 wherein each said first driving circuit includes at least one pull-up element and at least one pull-down element and said respective programming signal commands include at least two second programming signals which respectively cause a programmable circuit to control the drive strength of said at least one pull-up and at least one pull-down element.
Claim 27
Dependent Claim
26 words
A memory circuit as in claim 23 wherein said circuit portion for generating programming signal commands controls at least the timing for said first programming signal.
Claim 28
Dependent Claim
27 words
A memory circuit as in claim 23 wherein said circuit portion for generating programming signal commands controls at least the pulse width of said first programming signal.
Claim 29
Dependent Claim
27 words
A memory circuit as in claim 23 wherein said circuit portion for generating programming signal commands controls the timing and pulse width of said first programming signal.
Claim 30
Dependent Claim
34 words
A memory circuit as in claim 20 wherein said register is provided on a memory module and said circuit portion is respectively provided on a plurality of memory storage devices resident on said module.
Claim 31
Dependent Claim
54 words
A memory circuit as in claim 20 wherein said register and circuit portion are provided on a memory module and the output of said circuit portion is commonly provided to a plurality of memory storage devices resident on said module, said respective memory storage devices containing said driver circuit and said programmably altering circuit.
Claim 32
Dependent Claim
55 words
A memory circuit as in claim 1 wherein said driver circuit comprises at least one pair of a pull-up and pull-down element, at least one of said pull-up and pull-down elements of the pairs being a first transistor and said programmably altering circuit includes at least one second transistor in series with said first transistor.
Claim 33
Dependent Claim
50 words
A memory circuit as in claim 1 wherein said driver circuit comprises at least one pair of a pull-up and pull-down transistor and said programmably altering circuit includes at least one transistor in series with said pull-up transistor and at least another additional transistor in series with said pull-down transistor.
Claim 34
Dependent Claim
48 words
A memory circuit as in claim 1 , wherein said driver circuit comprises at least one paired pull-up and pull-down transistors, each of said transistors having a multiple finger gate, said programmably altering circuit providing control signals to said multiple finger gates of said pull-up and pull-down transistors.
Claim 35
Dependent Claim
66 words
A processor system comprising: a processor; and a memory system coupled to said processor through a bus system, at least one of said processor and memory system containing a data signal generator which comprises: a driver circuit for generating an output data signal on a data path; and a circuit for programmably altering a waveform shape of the output data signal generated by said driver circuit.
Claim 36
Dependent Claim
66 words
A processor system comprising: a processor; and a memory system coupled to said processor through a bus system, at least one of said processor and memory system containing a data signal generator which comprises: a driver circuit for generating an output data signal on a data path; and a circuit for programmably altering a waveform shape of the output data signal generated by said driver circuit.
Claim 37
Dependent Claim
21 words
A system as in claim 34 wherein said programmably altering circuit programmably alters the slew rate of said output data signal.
Claim 38
Dependent Claim
25 words
A system as in claim 34 wherein said programmably altering circuit programmably alters the amplitude of at least a portion of the output data signal.
Claim 39
Dependent Claim
29 words
A system as in claim 34 wherein said programmably altering circuit programmably alters the slew rate and the amplitude of at least a portion of said output data signal.
Claim 40
Dependent Claim
29 words
A system as in claim 34 wherein said programmably altering circuit alters the shape of at least one of a rising and falling edge of said output data signal.
Claim 41
Dependent Claim
24 words
A system as in claim 34 wherein said driver circuit and said programmably altering circuit are provided at a controller for said bus system.
Claim 42
Dependent Claim
27 words
A system as in claim 34 wherein said driver circuit and said programmably altering circuit are provided at a memory storage device coupled to said bus system.
Claim 43
Dependent Claim
25 words
A system as in claim 34 wherein said driver circuit and said programmably altering circuit are provided on a memory module of said memory system.
Claim 44
Dependent Claim
32 words
A system as in claim 41 wherein said driver circuit and a said programmably altering circuit are respectively provided at each of a plurality of memory storage devices on said memory module.
Claim 45
Dependent Claim
49 words
A system as in claim 41 wherein a said driver circuit is respectively provided at each of a plurality of memory storage devices on said memory module and said programmably altering circuit is provided on said memory module to commonly control the driver circuits of said memory storage devices.
Claim 46
Dependent Claim
40 words
A system as in claim 34 wherein said driver circuit comprises at least one paired pull-up and pull-down elements, at least one of which is controllable, said programmably altering circuit providing at least one control signal to said controllable element.
Claim 47
Dependent Claim
39 words
A system as in claim 34 wherein said driver circuit comprises at least one paired pull-up and pull-down driving elements and said programmably altering circuit provides control signals to said at least one paired pull-up and pull-down driving elements.
Claim 48
Dependent Claim
59 words
A system as in claim 34 wherein said driver circuit comprises a plurality of paired pull-up and pull-down driving elements, the outputs of said paired pull-up and pull-down driving elements being commonly connected to said data path, and said programmably altering circuit provides control signals to said paired pull-up and pull-down driving elements in accordance with applied program signals.
Claim 49
Dependent Claim
39 words
A system as in claim 46 wherein said programmably altering circuit comprises a plurality of programmable circuits each of which respectively controls paired pull-up and pull-down driving elements, each of said programmable circuits being responsive to respective program signals.
Claim 50
Dependent Claim
37 words
A system as in claim 47 wherein each of said programmable circuits is responsive to a first program signal to control whether a particular programmable circuit is operative to control a respective pair of pull-up-and pull-down elements.
Claim 51
Dependent Claim
47 words
A system as in claim 48 wherein each of said programmable circuits is responsive to at least one second program signal to control the drive strength of at least one of said pull up and pull down elements of a respective pair of pull-up and pull-down elements.
Claim 52
Dependent Claim
41 words
A system as in claim 49 wherein each of said programmable circuits is responsive to at least two second program signals to control the drive strength of said pull-up and pull-down elements of a respective pair of pull-up and pull-down elements.
Claim 53
Dependent Claim
38 words
A system as in claim 50 wherein each of said programmable circuits is responsive to a respective one of said second program signals to control the drive strength of a respective one of said pull-up and pull-down elements.
Claim 54
Dependent Claim
24 words
A system as in claim 34 further comprising a circuit responsive to programming signals for generating programming signal commands to said programmably altering circuit.
Claim 55
Dependent Claim
37 words
A system as in claim 52 wherein said programming signal command generating circuit comprises a register for receiving a digital programming command and a circuit portion for generating said programming signal commands based on said register contents.
Claim 56
Dependent Claim
59 words
A system as in claim 53 wherein said driver circuit comprises a plurality of first driver circuits having a common output on said data path, and said programmably altering circuit comprises a plurality of signal programmable circuits, each coupled to drive a respective first driver circuit, said circuit portion generating programming signal commands for said plurality of programmable circuits.
Claim 57
Dependent Claim
28 words
A system as in claim 54 wherein said circuit portion for generating programming signal commands generates respective programming signal commands for each of said plurality of programmable circuits.
Claim 58
Dependent Claim
51 words
A system as in claim 53 wherein said respective programming signal commands include a first programming signal which determines whether a respective programmable circuit is operative, and at least one second programming signal which causes said respective programmable circuit to determine a drive strength characteristic of a respective first driver circuit.
Claim 59
Dependent Claim
53 words
A system as in claim 56 , wherein each said first driving circuit includes at least one pull-up element and at least one pull-down element, at least one of said pull-up and pull-down elements being controllable and said respective programming signal commands include commands to control the drive strength of said controllable element.
Claim 60
Dependent Claim
59 words
A system as in claim 56 wherein each said first driver circuit includes at least one pull-up element and at least one pull-down element and said respective programming signal commands include at least two second programming signals which respectively cause a programmable circuit control the drive strength of said at least one pull-up and at least one pull-down element.
Claim 61
Dependent Claim
25 words
A system as in claim 56 wherein said circuit portion for generating programming signal commands controls at least the timing for said first programming signal.
Claim 62
Dependent Claim
26 words
A system as in claim 56 wherein said circuit portion for generating programming signal commands controls at least the pulse width of said first programming signal.
Claim 63
Dependent Claim
26 words
A system as in claim 56 wherein said circuit portion for generating programming signal commands controls the timing and pulse width of said first programming signal.
Claim 64
Dependent Claim
41 words
A system as in claim 53 wherein said register is provided on a memory module of said memory system and said circuit portion is respectively provided on a plurality of memory storage devices resident on said module of said memory system.
Claim 65
Dependent Claim
61 words
A system as in claim 53 wherein said register and circuit portion are provided on a memory module of said memory system and the output of said circuit portion is commonly provided to a plurality of memory storage devices resident on said module of said memory system, said respective memory storage devices containing said driver circuit and said programmably altering circuit.
Claim 66
Dependent Claim
54 words
A system as in claim 34 wherein said driver circuit comprises at least one pair of a pull-up and pull-down element, at least one of said pull-up and pull-down elements of the pairs being a first transistor and said programmably altering circuit includes at least one second transistor in series with said first transistor.
Claim 67
Dependent Claim
49 words
A system as in claim 34 wherein said driver circuit comprises at least one pair of a pull-up and pull-down transistor and said programmably altering circuit includes at least one transistor in series with said pull-up transistor and at least another additional transistor in series with said pull-down transistor.
Claim 68
Dependent Claim
16 words
A system as in claim 34 wherein said data signal generator is provided in said processor.
Claim 69
Dependent Claim
47 words
A system as in claim 34 , wherein said driver circuit comprises at least one paired pull-up and pull-down transistors, each of said transistors having a multiple finger gate, said programmably altering circuit providing control signals to said multiple finger gates of said pull-up and pull-down transistors.
Claim 70
Dependent Claim
105 words
A memory system comprising: a bus system; a memory controller coupled to said bus system; and at least one memory module coupled to said bus system, each said memory module containing at least one memory storage device; at least one of said memory controller and said memory module containing at least one signal generator for generating at least one data signal on a data path of said bus, said data signal generator comprising: a driver circuit for generating an output data signal on a data path; and a circuit for programmably altering a waveform shape of the output data signal generated by said driver circuit.
Claim 71
Dependent Claim
105 words
A memory system comprising: a bus system; a memory controller coupled to said bus system; and at least one memory module coupled to said bus system, each said memory module containing at least one memory storage device; at least one of said memory controller and said memory module containing at least one signal generator for generating at least one data signal on a data path of said bus, said data signal generator comprising: a driver circuit for generating an output data signal on a data path; and a circuit for programmably altering a waveform shape of the output data signal generated by said driver circuit.
Claim 72
Dependent Claim
22 words
A memory system as in claim 68 wherein said programmably altering circuit programmably alters the slew rate of said output data signal.
Claim 73
Dependent Claim
26 words
A memory system as in claim 68 wherein said programmably altering circuit programmably alters the amplitude of at least a portion of the output data signal.
Claim 74
Dependent Claim
30 words
A memory system as in claim 68 wherein said programmably altering circuit programmably alters the slew rate and the amplitude of at least a portion of said output data signal.
Claim 75
Dependent Claim
30 words
A memory system as in claim 68 wherein said programmably altering circuit alters the shape of at least one of a rising and falling edge of said output data signal.
Claim 76
Dependent Claim
26 words
A memory system as in claim 68 wherein said driver circuit and said programmably altering circuit are provided at said controller for said memory bus system.
Claim 77
Dependent Claim
27 words
A memory system as in claim 68 wherein said driver circuit and said programmably altering circuit are provided at a memory storage device of said memory system.
Claim 78
Dependent Claim
26 words
A memory system as in claim 68 wherein said driver circuit and said programmably altering circuit are provided on a memory module of said memory system.
Claim 79
Dependent Claim
33 words
A memory system as in claim 75 wherein said driver circuit and a said programmably altering circuit are respectively provided at each of a plurality of memory storage devices on said memory module.
Claim 80
Dependent Claim
50 words
A memory system as in claim 75 wherein a said driver circuit is respectively provided at each of a plurality of memory storage devices on said memory module and said programmably altering circuit is provided on said memory module to commonly control the driver circuits of said memory storage devices.
Claim 81
Dependent Claim
42 words
A memory system as in claim 68 , wherein said driver circuit comprises at least one paired pull-up and pull-down elements, at least one of which is controllable, said programmably altering circuit providing at least one control signal to said controllable element.
Claim 82
Dependent Claim
40 words
A memory system as in claim 68 wherein said driver circuit comprises at least one paired pull-up and pull-down driving elements and said programmably altering circuit provides control signals to said at least one paired pull-up and pull-down driving elements.
Claim 83
Dependent Claim
60 words
A memory system as in claim 68 wherein said driver circuit comprises a plurality of paired pull-up and pull-down driving elements, the outputs of said paired pull-up and pull-down driving elements being commonly connected to said data path, and said programmably altering circuit provides control signals to said paired pull-up and pull-down driving elements in accordance with applied program signals.
Claim 84
Dependent Claim
40 words
A memory system as in claim 80 wherein said programmably altering circuit comprises a plurality of programmable circuits each of which respectively controls paired pull-up and pull-down driving elements, each of said programmable circuits being responsive to respective program signals.
Claim 85
Dependent Claim
38 words
A memory system as in claim 81 wherein each of said programmable circuits is responsive to a first program signal to control whether a particular programmable circuit is operative to control a respective pair of pull-up-and pull-down elements.
Claim 86
Dependent Claim
48 words
A memory system as in claim 82 wherein each of said programmable circuits is responsive to at least one second program signal to control the drive strength of at least one of said pull up and pull down elements of a respective pair of pull-up and pull-down elements.
Claim 87
Dependent Claim
42 words
A memory system as in claim 83 wherein each of said programmable circuits is responsive to at least two second program signals to control the drive strength of said pull-up and pull-down elements of a respective pair of pull-up and pull-down elements.
Claim 88
Dependent Claim
39 words
A memory system as in claim 84 wherein each of said programmable circuits is responsive to a respective one of said second program signals to control the drive strength of a respective one of said pull-up and pull-down elements.
Claim 89
Dependent Claim
25 words
A memory system as in claim 68 further comprising a circuit responsive for programming signals for generating programming signal commands to said programmably altering circuit.
Claim 90
Dependent Claim
38 words
A memory system as in claim 86 wherein said programming signal command generating circuit comprises a register for receiving a digital programming command and a circuit portion for generating said programming signal commands based on said register contents.
Claim 91
Dependent Claim
59 words
A memory system as in claim 87 wherein said driver circuit comprises a plurality of first driver circuits having a common output on said data path, and said programmably altering circuit comprises a plurality of programmable circuits, each coupled to drive a respective first driver circuit, said circuit portion generating programming signal commands for said plurality of programmable circuits.
Claim 92
Dependent Claim
29 words
A memory system as in claim 88 wherein said circuit portion for generating programming signal commands generates respective programming signal commands for each of said plurality of programmable circuits.
Claim 93
Dependent Claim
52 words
A memory system as in claim 87 wherein said respective programming signal commands include a first programming signal which determines whether a respective programmable circuit is operative, and at least one second programming signal which causes said respective programmable circuit to determine a drive strength characteristic of a respective first driver circuit.
Claim 94
Dependent Claim
54 words
A memory system as in claim 90 , wherein each said first driver circuit includes at least one pull-up element and at least one pull-down element, at least one of said pull-up and pull-down elements being controllable and said respective programming signal commands include commands to control the drive strength of said controllable element.
Claim 95
Dependent Claim
61 words
A memory system as in claim 90 wherein each said first driving circuit includes at least one pull-up element and at least one pull-down element and said respective programming signal commands include at least two second programming signals which respectively cause a programmable circuit to control the drive strength of said at least one pull-up and at least one pull-down element.
Claim 96
Dependent Claim
26 words
A memory system as in claim 90 wherein said circuit portion for generating programming signal commands controls at least the timing for said first programming signal.
Claim 97
Dependent Claim
27 words
A memory system as in claim 90 wherein said circuit portion for generating programming signal commands controls at least the pulse width of said first programming signal.
Claim 98
Dependent Claim
27 words
A memory system as in claim 90 wherein said circuit portion for generating programming signal commands controls the timing and pulse width of said first programming signal.
Claim 99
Dependent Claim
38 words
A memory system as in claim 87 wherein said register is provided on a memory module of said memory system and said circuit portion is respectively provided on a plurality of memory storage devices resident on said module.
Claim 100
Dependent Claim
58 words
A memory system as in claim 87 wherein said register and circuit portion are provided on a memory module of said memory system and the output of said circuit portion is commonly provided to a plurality of memory storage devices resident on said module, said respective memory storage devices containing said driver circuit and said programmably altering circuit.
Claim 101
Dependent Claim
55 words
A memory system as in claim 68 wherein said driver circuit comprises at least one pair of a pull-up and pull-down element, at least one of said pull-up and pull-down elements of the pairs being a first transistor and said programmably altering circuit includes at least one second transistor in series with said first transistor.
Claim 102
Dependent Claim
50 words
A memory system as in claim 68 wherein said driver circuit comprises at least one pair of a pull-up and pull-down transistor and said programmably altering circuit includes at least one transistor in series with said pull-up transistor and at least another additional transistor in series with said pull-down transistor.
Claim 103
Dependent Claim
48 words
A memory system as in claim 68 , wherein said driver circuit comprises at least one paired pull-up and pull-down transistors, each of said transistors having a multiple finger gate, said programmably altering circuit providing control signals to said multiple finger gates of said pull-up and pull-down transistors.
Claim 104
Independent Claim
48 words
A method of generating a data signal on a data path of a bus, said method comprising: generating a data signal on said data path; and altering the waveform characteristics of at least a portion of said data signal in accordance with at least one applied program signal.
Claim 105
Independent Claim
48 words
A method of generating a data signal on a data path of a bus, said method comprising: generating a data signal on said data path; and altering the waveform characteristics of at least a portion of said data signal in accordance with at least one applied program signal.
Claim 106
Dependent Claim
25 words
A method as in claim 101 wherein a slew rate of said data signal is altered in accordance with at least one applied program signal.
Claim 107
Dependent Claim
31 words
A method as in claim 101 wherein at least the amplitude of at least a portion of said data signal is altered in accordance with at least one applied program signal.
Claim 108
Dependent Claim
34 words
A method as in claim 101 wherein a shape of at least one of a rising and falling edge of said data signal is altered in accordance with at least one applied program signal.
Claim 109
Dependent Claim
32 words
A method as in claim 101 wherein both the slew rate and amplitude of at least a portion of said data signal is altered in accordance with at least one applied program.
Claim 110
Dependent Claim
18 words
A method as in claim 101 wherein said method occurs at a controller of a memory bus system.
Claim 111
Dependent Claim
19 words
A method as in claim 101 wherein said method occurs at a memory module of a memory bus system.
Claim 112
Dependent Claim
19 words
A method as in claim 107 wherein said method occurs at a memory storage device of said memory module.
Claim 113
Independent Claim
74 words
A method of generating a data signal on a data path of a bus, said method comprising: determining how a data signal applied to a bus is degraded when traveling from a first generating device to a second receiving device coupled to said bus; and programmably altering a waveform shape of said data signal at said first generating device to reduce the degradation of said data signal as received at said second receiving device.
Claim 114
Independent Claim
74 words
A method of generating a data signal on a data path of a bus, said method comprising: determining how a data signal applied to a bus is degraded when traveling from a first generating device to a second receiving device coupled to said bus; and programmably altering a waveform shape of said data signal at said first generating device to reduce the degradation of said data signal as received at said second receiving device.
Claim 115
Dependent Claim
22 words
A method as in claim 109 further comprising programmably altering at least the slew rate of a portion of said data signal.
Claim 116
Dependent Claim
21 words
A method as in claim 109 further comprising programmably altering at least the amplitude of a portion of said data signal.
Claim 117
Dependent Claim
26 words
A method as in claim 109 further comprising programmably altering the shape of at least one of a rising and falling edge of said data signal.
Claim 118
Dependent Claim
25 words
A method as in claim 109 further comprising programmably altering both the slew rate and amplitude of at least a portion of said data signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-07-02 | 2005-01-01 | 2005-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-07-02 | 2009-01-01 | 2009-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-07-02 | 2013-01-01 | 2013-07-03 | $7700.00 | Window Closed / Lapsed |