Patent US6243778B1 successfully refreshed from Google Patents.
US6243778B1
Expired / Lapsed
US
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Transaction interface for a data communication system
Assignee: STMicroelectronics lnc USA
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Filing: 1998-10-13
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Granted: 2001-06-05
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Expires: 2018-10-13
Abstract
Abstract A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. Each task operates according to a state machine progression. The transaction interface accepts data information from the tasks and forms data packets for delivery to the 1394 bus. The data packets are initially sent via an associated hardware register, but if busy, the transaction interface polls for other available registers. In addition, all queued transactions are loaded into registers in the most expedient manner.
Inventors
- 👤 Anthony Fung
- 👤 Peter Groz
- 👤 Jim C. Hsu
- 👤 Danny K. Hui
- 👤 Harry S. Hvostov
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:50
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40052; H04L12/40123; H04L12/40117; H04L49/00; H04L49/90
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
167 words
A transport protocol interface system for a serial bus, the system comprising: a transaction interface for coordinating communications to and from the bus, comprising: a first queue structured to accept one or more message control blocks, each message control block containing organized data and to accept one or more data packets; a conversion engine structured to read the message control blocks and convert the organized data into data packets and to read the one or more data packets and convert the data packets into message control blocks; an input port structured to receive data packets from the bus, and an output port structured to pass data packets to the bus; the system further comprising at least one task structured to communicate with the transaction interface to receive and transmit message control blocks; and a service provider structured to communicate with the at least one task, the service provider configured to schedule task requests received from the at least one task and to allocate system resources including memory.
Claim 2
Dependent Claim
167 words
A transport protocol interface system for a serial bus, the system comprising: a transaction interface for coordinating communications to and from the bus, comprising: a first queue structured to accept one or more message control blocks, each message control block containing organized data and to accept one or more data packets; a conversion engine structured to read the message control blocks and convert the organized data into data packets and to read the one or more data packets and convert the data packets into message control blocks; an input port structured to receive data packets from the bus, and an output port structured to pass data packets to the bus; the system further comprising at least one task structured to communicate with the transaction interface to receive and transmit message control blocks; and a service provider structured to communicate with the at least one task, the service provider configured to schedule task requests received from the at least one task and to allocate system resources including memory.
Claim 3
Dependent Claim
33 words
The system of claim 1 wherein the transaction interface comprises at least one transmit bay having a hardware register, and wherein data packets are written to the hardware register in the transmit bay.
Claim 4
Dependent Claim
38 words
The system of claim 2 wherein the transaction interface is structured so that, after the data packets are written to the hardware register, a trigger bit is set to indicate that there is data in the transmit bay.
Claim 5
Dependent Claim
52 words
The system of claim 1 , wherein the transaction interface further comprises: a second queue structured to accept message control blocks having a higher priority than blocks accepted at the first queue; a third queue structured to accept message control blocks having a higher priority than blocks received at the second queue.
Claim 6
Dependent Claim
83 words
The system of claim 1 , wherein the transaction interface further comprises a plurality of transmit bays and output ports, wherein each of the transmit bays are related to a respective one of the output ports, and wherein each output port is structured to, for each data packet, attempt to pass the data packet to its respective transmit bay, and if busy, repeatedly attempt to pass the data packet to another transmit bay until a transmit bay is located that is not busy.
Claim 7
Dependent Claim
23 words
The system of claim 5 wherein the total number of output ports and total number transmit bays in the transaction interface is three.
Claim 8
Dependent Claim
10 words
The system of claim 1 further comprising a DMA channel.
Claim 9
Dependent Claim
12 words
The system of claim 1 further comprising a payload data transmit bay.
Claim 10
Dependent Claim
36 words
The system of claim 8 wherein data comprising a lock response according to a 1394 protocol is sent by a node on the serial bus using both the transmit bay and the payload data transmit bay.
Claim 11
Dependent Claim
21 words
The system of claim 1 , further including a receive hardware bay structured to receive data packets from the serial bus.
Claim 12
Dependent Claim
19 words
The system of claim 1 wherein the message control blocks received by the queue are Transaction Message Control blocks.
Claim 13
Dependent Claim
142 words
In a node on a serial bus, a transaction interface system comprising: a transaction interface, comprising: a queue structured to receive one or more message control blocks from at least one task component associated with the node, each message control block containing organized data; a set of logical processes structured to read the message control blocks and convert the organized data into data packets; and at least two output ports each related to a respective transmit bay, and each structured to pass the data packets to its respective transmit bay or to another transmit bay to be placed on the bus; the system further comprising a service kernal associated with the at least one task component and configured to schedule and dispatch tasks and services within the node called by the one or more message control blocks and to allocate memory resources.
Claim 14
Dependent Claim
142 words
In a node on a serial bus, a transaction interface system comprising: a transaction interface, comprising: a queue structured to receive one or more message control blocks from at least one task component associated with the node, each message control block containing organized data; a set of logical processes structured to read the message control blocks and convert the organized data into data packets; and at least two output ports each related to a respective transmit bay, and each structured to pass the data packets to its respective transmit bay or to another transmit bay to be placed on the bus; the system further comprising a service kernal associated with the at least one task component and configured to schedule and dispatch tasks and services within the node called by the one or more message control blocks and to allocate memory resources.
Claim 15
Dependent Claim
18 words
The transaction interface system of claim 12 wherein the data packets are written to a transmit bay register.
Claim 16
Dependent Claim
39 words
The transaction interface system of claim 12 , further comprising: a plurality of priority queues in the transaction interface and structured to accept message control blocks having a higher priority than the message control blocks accepted at the queue.
Claim 17
Dependent Claim
65 words
The transaction interface system of claim 12 , wherein each of the transmit bays are related to a respective output port, and, before one of the output ports passes data packets to the transmit bay, the set of logical processes checks a data structure to determine which of the transmit bays of the transaction interface, if any, are free to have data written to it.
Claim 18
Dependent Claim
26 words
The transaction interface system of claim 15 wherein the set of logical processes checks the output port's respective transmit bay before checking any other transmit bays.
Claim 19
Dependent Claim
25 words
The transaction interface system of claim 12 wherein the total number of output ports and total number transmit bays in the transaction interface is three.
Claim 20
Dependent Claim
15 words
The transaction interface system of claim 12 wherein the hardware further comprises a DMA channel.
Claim 21
Dependent Claim
23 words
The transaction interface system of claim 12 , further including a hardware receiving bay structured to receive data packets from the serial bus.
Claim 22
Independent Claim
98 words
A method of transacting data to a serial bus comprising: accepting, at a queue, message control blocks from one or more task components including data destined to be sent to the bus; formatting the data to be sent into one or more packets; formatting other data contained within the message control block into packet headers for the packets; writing the packets and the packet headers to the serial bus via a hardware interface; and communicating to the hardware interface that the packets had been written and, when the hardware interface is busy, polling for other available hardware interfaces.
Claim 23
Independent Claim
98 words
A method of transacting data to a serial bus comprising: accepting, at a queue, message control blocks from one or more task components including data destined to be sent to the bus; formatting the data to be sent into one or more packets; formatting other data contained within the message control block into packet headers for the packets; writing the packets and the packet headers to the serial bus via a hardware interface; and communicating to the hardware interface that the packets had been written and, when the hardware interface is busy, polling for other available hardware interfaces.
Claim 24
Dependent Claim
97 words
The method of claim 20 wherein writing the packets and the packet headers to a hardware interface and communicating to the serial interface comprises: at one of a plurality of output nodes, evaluating a data structure to determine if a respective one of a plurality of hardware registers are currently available; if the respective hardware register is available, write a data packet to the hardware register; and if the respective hardware register is not available, sequentially evaluate all of the hardware registers, in sequence, until a hardware register that does not have data in it is found.
Claim 25
Dependent Claim
36 words
The method of claim 20 wherein accepting message control blocks comprises receiving message control blocks at one of a plurality of queues, each queue designated as having a different priority for execution than the other queues.
Claim 26
Dependent Claim
35 words
The method of claim 20 wherein formatting the data to be sent into one or more packets comprises encapsulation data in blocks, the size of which are limited by a speed of the serial bus.
Claim 27
Dependent Claim
23 words
The method of claim 20 wherein the step of communication to the hardware interface comprises setting a trigger bit in the hardware interface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-06-04 | 2004-12-04 | 2005-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-06-04 | 2008-12-04 | 2009-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-06-04 | 2012-12-04 | 2013-06-05 | $7700.00 | Window Closed / Lapsed |