Controlled impedance bus and method for a computer system

Claim 2

A plurality of multi-layer circuit substrates for a computer system having an integral bus portion comprising: a dielectric filler between each circuit substrate; each circuit substrate including: a first dielectric substrate; a first device signal trace layer including a first bus reference plane on one side of the first dielectric substrate; and a device reference plane layer on another side of the first dielectric substrate opposite the one side; a second dielectric substrate formed on the device reference planer layer; a second device signal trace layer including a second bus reference plane formed on a side of the second dielectric substrate opposite the device reference plane layer; and the device reference plane layer being patterned to include at least one device reference plane, at least two guard bands, and a bus signal trace formed between the guard bands.

Claim 3

The multi-layer circuit substrate of claim 1 further including means for electrically coupling each of the bus reference planes to at least one of the guard bands.

Claim 4

The multi-layer circuit substance of claim 2 further including a plurality of conductive vias extending through the guard bands and bus reference planes.

Claim 5

The multi-layer circuit substrate of claim 1 wherein the first and second dielectric substrates have a dielectric constant of from about 4.0 to about 4.5.

Claim 6

The multi-layer circuit substrate of claim 1 wherein the bus reference planes are spaced apart from each other by a distance of about 9 mils.

Claim 7

The multi-layer circuit substrate of claim 1 wherein the bus signal trace is spaced approximately equidistantly from each of the adjacent bus reference planes.

Claim 8

The multi-layer circuit substrate of claim 1 wherein the bus has an impedance of from about 25 ohms to about 31 ohms.

Claim 9

The multi-layer circuit substrate of claim 1 wherein at least one of the device signal trace layers is patterned to include at least one device signal trace.

Claim 10

The multi-layer circuit substrate of claim 1 wherein one of the device signal trace layers is patterned to include at least one device signal trace and the other device signal trace layer is patterned to include at least one reference voltage plane.

Claim 11

A printed circuit comprising: a pair of multi-layer circuit substrates; a dielectric filler between each circuit substrate; each circuit substrate including: a first dielectric substrate; a first device signal trace layer including a first bus reference plane on one side of the first dielectric substrate; and a device reference plane layer on another side of the first dielectric substrate opposite the one side; a second dielectric substrate formed on the device reference plane layer; a second device signal trace layer including a second bus reference plane formed on a side of the second dielectric substrate opposite the device reference plane layer; and the device reference plane layer being patterned to include at least one device reference plane, at least two guard bands, and a bus signal trace formed between the guard bands.

Claim 12

A printed circuit comprising: a pair of multi-layer circuit substrates; a dielectric filler between each circuit substrate; each circuit substrate including: a first dielectric substrate; a first device signal trace layer including a first bus reference plane on one side of the first dielectric substrate; and a device reference plane layer on another side of the first dielectric substrate opposite the one side; a second dielectric substrate formed on the device reference plane layer; a second device signal trace layer including a second bus reference plane formed on a side of the second dielectric substrate opposite the device reference plane layer; and the device reference plane layer being patterned to include at least one device reference plane, at least two guard bands, and a bus signal trace formed between the guard bands.

Claim 13

The printed circuit board of claim 10 further including means for electrically coupling each of the bus reference planes to at least one of the guard bands.

Claim 14

The printed circuit board of claim 11 further including a plurality of conductive vias extending through the guard bands and bus reference planes.

Claim 15

The printed circuit board of claim 10 wherein the first and second dielectric substrates have a dielectric constant of from about 4.0 to about 4.5.

Claim 16

The printed circuit board of claim 10 wherein the bus reference planes are spaced apart from each other by a distance of about 9 mils.

Claim 17

The printed circuit board of claim 10 wherein the bus signal trace is spaced approximately equidistantly from each of the adjacent bus reference planes.

Claim 18

The printed circuit board of claim 10 wherein the bus has an impedance of from about 25 ohms to about 31 ohms.

Claim 19

The printed circuit board of claim 10 wherein at least one of the device signal trace layers is patterned to include at least one device signal trace.

Claim 20

The printed circuit board of claim 10 wherein one of the device signal trace layers is patterned to include at least one device signal trace and the other device signal trace layer is patterned to include at least one reference voltage plane.

Claim 21

A computer system, comprising: a microprocessor mounted on a first printed circuit substrate; an input coupled to provide input to the microprocessor; a mass storage coupled to the microprocessor; a video controller coupled to the microprocessor; a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, the memory mounted on a second printed circuit substrate; and a bus coupled to the memory; a dielectric filler between the first circuit substrate and the second circuit substrate; each circuit substrate including: a first dielectric substrate; a first device signal trace layer including a first bus reference plane on one side of the first dielectric substrate; and a device reference plane layer on another side of the first dielectric substrate opposite the one side; a second dielectric substrate formed on the device reference plane layer; a second device signal trace layer including a second bus reference plane formed on a side of the second dielectric substrate opposite the device reference plane layer; and the device reference plane layer being patterned to include at least one device reference plane, at least two guard bands, and a bus signal trace formed between the guard bands.

Claim 22

A computer system, comprising: a microprocessor mounted on a first printed circuit substrate; an input coupled to provide input to the microprocessor; a mass storage coupled to the microprocessor; a video controller coupled to the microprocessor; a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, the memory mounted on a second printed circuit substrate; and a bus coupled to the memory; a dielectric filler between the first circuit substrate and the second circuit substrate; each circuit substrate including: a first dielectric substrate; a first device signal trace layer including a first bus reference plane on one side of the first dielectric substrate; and a device reference plane layer on another side of the first dielectric substrate opposite the one side; a second dielectric substrate formed on the device reference plane layer; a second device signal trace layer including a second bus reference plane formed on a side of the second dielectric substrate opposite the device reference plane layer; and the device reference plane layer being patterned to include at least one device reference plane, at least two guard bands, and a bus signal trace formed between the guard bands.

Claim 23

The computer system of claim 19 wherein the bus includes a first portion on the first printed circuit substrate and a second portion on the second printed circuit substrate the first and second portions of the bus being electrically connected by a connector.

Claim 24

The computer system of claim 19 further including means for electrically coupling each of the bus reference planes to at least one of the guard bands.

Claim 25

The computer system of claim 21 further including a plurality of conductive vias extending through the guard bands and bus reference planes.

Claim 26

The computer system of claim 19 wherein the first and second dielectric substrates have a dielectric constant of from about 4.0 to about 4.5.

Claim 27

The computer system of claim 19 wherein the bus reference planes are spaced apart from each other by a distance of about 9 mils.

Claim 28

The computer system of claim 19 wherein the bus signal trace is spaced approximately equidistantly from each of the adjacent bus reference planes.

Claim 29

The computer system of claim 19 wherein the bus has an impedance of from about 25 ohms to about 31 ohms.

Claim 30

The computer system of claim 19 wherein at least one of the device signal trace layers is patterned to include at least one device signal trace.

Claim 31

The computer system of claim 19 wherein one of the device signal trace layers is patterned to include at least one device signal trace and the other device signal trace layer is patterned to include at least one reference voltage plane.

Claim 34

The method of claim 29 further including the step of forming means for electrically coupling each of the bus reference planes to at least one of the guard bands.

Claim 35

The method of claim 29 wherein the means for electrically coupling includes a plurality of conductive vias extending through the guard bands and bus reference planes.

Claim 36

The method of claim 29 wherein at least one of the device signal trace layers is patterned to include at least one device signal trace.

Claim 37

The method of claim 29 wherein one of the device signal trace layers is patterned to include at least one device signal trace and the other device signal trace layer is patterned to include at least one reference voltage plane.