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US6232806B1
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Multiple-mode clock distribution apparatus and method with adaptive skew compensation
Assignee: International Business Machines Corp
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Filing: 1998-10-21
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Granted: 2001-05-15
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Expires: 2018-10-21
Abstract
Abstract An apparatus and method for distributing a clock signal within circuitry disposed on a number of separate system cards includes a first system card that generates a reference clock signal representative of a fixed delay of a system clock signal. A number of variable clock signals are produced using the system clock signal. Each of a number of system cards separate from the first system card receive one of the variable clock signals. A delay associated with the reference clock signal is typically longer than a delay associated with each of the variable clock signals. The phase of each of the variable clock signals is adjusted to a substantially in-phase relationship with respect to the reference clock signal in response to a phase difference between the reference clock signal an output signal received from each of the separate system cards. Producing each of the variable clock signals may involve selecting between a first delay line and a second delay line, and then producing the variable delay signal using the selected first or second delay line. A delay factor of the non-selected first or second delay line may be changed by varying a resistance and a current of one or more delay elements of the non-selected first or second delay lines. The circuitry is selectably operable in a slave or buffer-type clock repowering mode or an adaptive mode. The variable clock signals and the output signals may respectively comprise low voltage differential signals (LVDS) or CMOS level signals.
Inventors
- 👤 Dana Marie Woeste
- 👤 James David Strom
- 👤 Bruce George Rudolph
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:51
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
109 words
A method of distributing a signal to a plurality of receiving devices, comprising: producing a plurality of delayed signals each having a respective delay relative to a system clock signal; transmitting each of the delayed signals to a respective one of the plurality of receiving devices; and adjusting the delay of each of the delayed signals using a reference signal having a delay relative to the system clock signal and an output signal provided by each receiving device such that each of the delayed signals is received by the respective receiving devices at approximately the same time wherein the reference signal has longer delay time than the delayed signals.
Claim 2
Independent Claim
109 words
A method of distributing a signal to a plurality of receiving devices, comprising: producing a plurality of delayed signals each having a respective delay relative to a system clock signal; transmitting each of the delayed signals to a respective one of the plurality of receiving devices; and adjusting the delay of each of the delayed signals using a reference signal having a delay relative to the system clock signal and an output signal provided by each receiving device such that each of the delayed signals is received by the respective receiving devices at approximately the same time wherein the reference signal has longer delay time than the delayed signals.
Claim 3
Dependent Claim
23 words
The method of claim 1 , wherein the reference signal comprises a signal having a fixed delay relative to the system clock signal.
Claim 4
Dependent Claim
51 words
The method of claim 1 , wherein adjusting each of the delayed signals comprises adjusting a phase of each of the delayed signals to a substantially in-phase relationship with respect to the reference signal in response to a phase difference between the reference signal and each of the respective output signals.
Claim 5
Dependent Claim
13 words
The method of claim 1 , wherein the output signals comprise data signals.
Claim 6
Dependent Claim
24 words
The method of claim 1 , wherein the delayed signals and the output signals respectively comprise low voltage differential signals or CMOS level signals.
Claim 7
Dependent Claim
27 words
The method of claim 1 , wherein the method of distributing the signal is selectable between an adaptive mode of operation and a slave mode of operation.
Claim 8
Dependent Claim
26 words
The method of claim 1 , wherein a delay associated with the reference signal is longer than a delay associated with each of the delayed signals.
Claim 9
Dependent Claim
25 words
The method of claim 1 , wherein adjusting the delay of the delayed signals comprises digitally adjusting the phase of each of the delayed signals.
Claim 10
Dependent Claim
79 words
The method of claim 1 , wherein producing each of the delayed signals comprises: selecting between one of a first delay line or a second delay line; producing the delayed signal using the selected first or second delay line; and changing a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines.
Claim 11
Dependent Claim
24 words
The method of claim 9 , further comprising providing a reference voltage having a substantially constant amplitude to the one or more delay elements.
Claim 12
Dependent Claim
159 words
An adaptive clock distribution circuit, comprising: a master module comprising a fixed delay line and a plurality of variable delay line circuits, the fixed delay line and each of the variable delay line circuits receiving a system clock signal, the fixed delay line producing a delayed clock signal; a primary slave module coupled to the master module, the primary slave module receiving the delayed clock signal from the fixed delay line and producing a reference clock signal; and a plurality of secondary slave modules each coupled to one or more logic devices, each of the secondary slave modules receiving a variable clock signal from one of the variable delay line circuits and producing a slave output signal, the master module adjusting the variable clock signal received by each of the secondary slave modules so as to substantially align with the reference clock signal in response to a phase difference between respective slave output signals and the reference clock signal.
Claim 13
Dependent Claim
159 words
An adaptive clock distribution circuit, comprising: a master module comprising a fixed delay line and a plurality of variable delay line circuits, the fixed delay line and each of the variable delay line circuits receiving a system clock signal, the fixed delay line producing a delayed clock signal; a primary slave module coupled to the master module, the primary slave module receiving the delayed clock signal from the fixed delay line and producing a reference clock signal; and a plurality of secondary slave modules each coupled to one or more logic devices, each of the secondary slave modules receiving a variable clock signal from one of the variable delay line circuits and producing a slave output signal, the master module adjusting the variable clock signal received by each of the secondary slave modules so as to substantially align with the reference clock signal in response to a phase difference between respective slave output signals and the reference clock signal.
Claim 14
Dependent Claim
14 words
The circuit of claim 11 , wherein the slave output signals comprise data signals.
Claim 15
Dependent Claim
26 words
The circuit of claim 11 , wherein the variable clock signals and the slave output signals respectively comprise low voltage differential signals or CMOS level signals.
Claim 16
Dependent Claim
19 words
The circuit of claim 11 , wherein the primary slave module is coupled to one or more logic devices.
Claim 17
Dependent Claim
27 words
The circuit of claim 11 , wherein the variable clock signal received by each of the secondary slave modules is used for clocking the respective logic devices.
Claim 18
Dependent Claim
21 words
The circuit of claim 11 , wherein the circuit is disposed on a signal wafer or on a plurality of wafers.
Claim 19
Dependent Claim
23 words
The circuit of claim 11 , wherein the circuit is operative in a slave mode of operation or an adaptive mode of operation.
Claim 20
Dependent Claim
28 words
The circuit of claim 11 , wherein fixed delay line has a delay factor longer than a delay factor associated with each of the variable delay line circuits.
Claim 21
Dependent Claim
71 words
The circuit of claim 11 , wherein the master module further comprises a plurality of control circuits and a plurality of phase detectors, each of the control circuits coupled to one of the variable delay line circuits and one of the phase detectors, and each of the phase detectors receiving the reference clock signal from the primary slave module and a slave output signal from one of the secondary slave modules.
Claim 22
Dependent Claim
37 words
The circuit of claim 11 , wherein each of the variable delay line circuits comprises a first delay line, a second delay line, and a multiplexer coupled to respective outputs of the first and second delay lines.
Claim 23
Dependent Claim
181 words
The circuit of claim 11 , wherein each of the variable delay line circuits comprises: a first delay line including a plurality of delay elements; a second delay line including a plurality of delay elements; a multiplexer coupled to respective outputs of the first and second delay lines, the multiplexer selectively coupling the output of one of the first or second delay lines to an output of the multiplexer; a reference voltage source coupled to each of the delay elements, the reference voltage source providing a reference voltage at a substantially constant amplitude to each of the delay elements; and a control circuit coupled to the multiplexer and the first and second delay lines, the control circuit controlling the multiplexer so as to produce a variable clock signal at the multiplexer output using one of the first or second delay lines, and changing a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines.
Claim 24
Dependent Claim
15 words
The circuit of claim 11 , wherein the circuit is a digital clock distribution circuit.
Claim 25
Dependent Claim
100 words
A circuit for distributing a signal, comprising: means for producing a plurality of signals each having a respective delay; means for transmitting each of the delayed signals to a respective one of the plurality of receiving devices; and means for adjusting the delay of each of the delayed signals using a reference signal and an output signal provided by each receiving device such that each of the delayed signals is received by the respective receiving devices at approximately the same time, a delay associated with the reference signal being longer than a delay associated with each of the delayed signals.
Claim 26
Dependent Claim
100 words
A circuit for distributing a signal, comprising: means for producing a plurality of signals each having a respective delay; means for transmitting each of the delayed signals to a respective one of the plurality of receiving devices; and means for adjusting the delay of each of the delayed signals using a reference signal and an output signal provided by each receiving device such that each of the delayed signals is received by the respective receiving devices at approximately the same time, a delay associated with the reference signal being longer than a delay associated with each of the delayed signals.
Claim 27
Dependent Claim
13 words
The circuit of claim 23 , wherein the output signals comprise data signals.
Claim 28
Dependent Claim
24 words
The circuit of claim 23 , wherein the delayed signals and the output signals respectively comprise low voltage differential signals or CMOS level signals.
Claim 29
Dependent Claim
24 words
The circuit of claim 23 , wherein the circuit is selectably operable in a slave mode of operation or an adaptive mode of operation.
Claim 30
Dependent Claim
23 words
The circuit of claim 23 , wherein the adjusting means comprises means for digitally adjusting the phase of each of the delayed signals.
Claim 31
Dependent Claim
103 words
The circuit of claim 23 , wherein the producing means comprises: means for selecting between one of a first delay line or a second delay line of a plurality of delay line circuits; means for producing each of the delayed signals using the selected first or second delay line of a respective delay line circuit; and means for changing a delay factor of the other one of the first or second delay lines of the respective delay line circuit by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines.
Claim 32
Dependent Claim
26 words
The circuit of claim 28 , further comprising means for providing a reference voltage having a substantially constant amplitude to the one or more delay elements.
Claim 33
Dependent Claim
193 words
A computer system, comprising: a central processing unit; system memory coupled to the central processing unit; an input/output interface coupled to the central processing unit for interfacing with one or more external components; and a clock signal distribution circuit comprising: a master module comprising a fixed delay line and a plurality of variable delay line circuits, the fixed delay line and each of the variable delay line circuits receiving a system clock signal, the fixed delay line producing a delayed clock signal; a primary slave module coupled to the master module, the primary slave module receiving the delayed clock signal from the fixed delay line and producing a reference clock signal; and a plurality of secondary slave modules each coupled to one or more logic devices, each of the secondary slave modules receiving a variable clock signal from one of the variable delay line circuits and producing a slave output signal, the master module adjusting the variable clock signal received by each of the secondary slave modules so as to substantially align with the reference clock signal in response to a phase difference between respective slave output signals and the reference clock signal.
Claim 34
Dependent Claim
193 words
A computer system, comprising: a central processing unit; system memory coupled to the central processing unit; an input/output interface coupled to the central processing unit for interfacing with one or more external components; and a clock signal distribution circuit comprising: a master module comprising a fixed delay line and a plurality of variable delay line circuits, the fixed delay line and each of the variable delay line circuits receiving a system clock signal, the fixed delay line producing a delayed clock signal; a primary slave module coupled to the master module, the primary slave module receiving the delayed clock signal from the fixed delay line and producing a reference clock signal; and a plurality of secondary slave modules each coupled to one or more logic devices, each of the secondary slave modules receiving a variable clock signal from one of the variable delay line circuits and producing a slave output signal, the master module adjusting the variable clock signal received by each of the secondary slave modules so as to substantially align with the reference clock signal in response to a phase difference between respective slave output signals and the reference clock signal.
Claim 35
Dependent Claim
26 words
The system of claim 30 , wherein the variable clock signals and the slave output signals respectively comprise low voltage differential signals or CMOS level signals.
Claim 36
Dependent Claim
21 words
The system of claim 30 , wherein the circuit is disposed on a signal wafer or on a plurality of wafers.
Claim 37
Dependent Claim
23 words
The system of claim 30 , wherein the circuit is operative in a slave mode of operation or an adaptive mode of operation.
Claim 38
Dependent Claim
28 words
The system of claim 30 , wherein fixed delay line has a delay factor longer than a delay factor associated with each of the variable delay line circuits.
Claim 39
Dependent Claim
71 words
The circuit of claim 30 , wherein the master module further comprises a plurality of control circuits and a plurality of phase detectors, each of the control circuits coupled to one of the variable delay line circuits and one of the phase detectors, and each of the phase detectors receiving the reference clock signal from the primary slave module and a slave output signal from one of the secondary slave modules.
Claim 40
Dependent Claim
37 words
The system of claim 30 , wherein each of the variable delay line circuits comprises a first delay line, a second delay line, and a multiplexer coupled to respective outputs of the first and second delay lines.
Claim 41
Dependent Claim
182 words
The system of claim 30 , wherein each of the variable delay line circuits comprises: a first delay line including a plurality of delay elements; a second delay line including a plurality of delay elements; a multiplexer coupled to respective outputs of the first and second delay lines, the multiplexer selectively coupling the output of one of the first or second delay line s to an output of the multiplexer; a reference voltage source coupled to each of the delay elements, the reference voltage source providing a reference voltage at a substantially constant amplitude to each of the delay elements; and a control circuit coupled to the multiplexer and the first and second delay lines, the control circuit controlling the multiplexer so as to produce a variable clock signal at the multiplexer output using one of the first or second delay lines, and changing a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-14 | 2004-11-13 | 2005-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-14 | 2008-11-13 | 2009-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-14 | 2012-11-13 | 2013-05-15 | $7700.00 | Window Closed / Lapsed |