US6232589B1
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Single polysilicon CMOS pixel with extended dynamic range
Assignee: DYNAMAX IMAGING LLC
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Filing: 1999-01-19
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Granted: 2001-05-15
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Expires: 2019-01-19
Abstract
Abstract A new method of forming a photogate structure called a “Charge Snare Device” (CSD) uses only a single layer of polysilicon where prior art methods used two or more layers for constructing the gate nodes. Typical CCD structures utilize three layers of polysilicon and CID structures utilize two layers of polysilicon and neither of the prior art structures are suitable for standard sub micron processes. The new CSD device allows biasing of the photogate to the full potential that the process will allow for greater full well for a given pixel size and therefore an improved signal to noise ratio. Charge transfer between the collection site and the sense site isn't controlled as in all previous devices, rather the collection site is completely enclosed by the sense site, effectively snaring all collected photon generated charge as it diffuses and drifts to the sense site. The new photogate structure is suitable for passive pixels, Active Pixel Sensors (APS) or Active Column Sensors (ACS).
Inventors
- 👤 Matthew A. Pace
- 👤 Jeffrey J. Zamowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:06
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/80; H10F39/803; H10F39/8037; H10F39/80373
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
37 words
A charge snare device, comprising: a substrate; and a plurality of pixels on the substrate, each pixel comprising a charge collection gate; and a sense gate, the sense gate at least substantially surrounding the charge collection gate.
Claim 2
Dependent Claim
37 words
A charge snare device, comprising: a substrate; and a plurality of pixels on the substrate, each pixel comprising a charge collection gate; and a sense gate, the sense gate at least substantially surrounding the charge collection gate.
Claim 3
Dependent Claim
17 words
The charge snare device of claim 1 , the sense gate totally surrounding the charge collection gate.
Claim 4
Dependent Claim
28 words
The charge snare device of claim 1 , each pixel further comprising a lateral drain, the lateral drain providing a complete lateral block preventing charge transfer between pixels.
Claim 5
Dependent Claim
21 words
The charge snare device of claim 1 , the sense gate and charge collection gate having a spaced apart, non-overlapping relationship.
Claim 6
Dependent Claim
30 words
The charge snare device of claim 1 , further comprising a light blocking layer for each pixel, the light blocking layer being formed to block light to the sense gate.
Claim 7
Dependent Claim
25 words
The charge snare device of claim 1 , wherein the sense gate and the charge collection gate are formed from a single layer of material.
Claim 8
Dependent Claim
21 words
The charge snare device of claim 6 , wherein the single layer of material is a layer of CMOS compatible material.
Claim 9
Dependent Claim
16 words
The charge snare device of claim 7 , wherein the single layer of material is polysilicon.
Claim 10
Dependent Claim
17 words
The charge snare device of claim 5 , wherein the light blocking layer is formed of metal.
Claim 11
Dependent Claim
33 words
The charge snare device of claim 1 , wherein the charge collection gate and the sense gate each can be biased to the limits imposed by the material from which each is formed.
Claim 12
Dependent Claim
20 words
The charge snare device of claim 1 , wherein each of the plurality of pixels is a passive pixel sensor.
Claim 13
Dependent Claim
20 words
The charge snare device of claim 1 , wherein each of the plurality of pixels is an active pixel sensor.
Claim 14
Dependent Claim
20 words
The charge snare device of claim 1 , wherein each of the plurality of pixels is an active column sensor.
Claim 15
Dependent Claim
21 words
The charge snare device of claim 3 , wherein the lateral drain is an N-well in which control FETs are formed.
Claim 16
Dependent Claim
69 words
A imager array, comprising: a semiconductor substrate; and a a matrix of pixels formed in the semiconductor substrate, each pixel having a first portion for generating charge upon stimulation by radiant energy second portion for sensing the charge, and a third portion for reading and erasing the charge, wherein the second portion is formed on the surface of the semiconductor substrate so as to totally surround the first portion.
Claim 17
Dependent Claim
69 words
A imager array, comprising: a semiconductor substrate; and a a matrix of pixels formed in the semiconductor substrate, each pixel having a first portion for generating charge upon stimulation by radiant energy second portion for sensing the charge, and a third portion for reading and erasing the charge, wherein the second portion is formed on the surface of the semiconductor substrate so as to totally surround the first portion.
Claim 18
Dependent Claim
14 words
The imager array of claim 15 , wherein the third portion comprises an N-well.
Claim 19
Dependent Claim
20 words
The imager array of claim 16 , wherein a video FET and a bias FET are formed in the N-well.
Claim 20
Dependent Claim
58 words
The imager array of claim 17 , wherein the gate of the bias FET is driven by a row selection signal, one of the source and drain of the bias FET is driven by a sense bias signal, and the other of the source and drain of the bias FET is tied to the charge sensing second portion.
Claim 21
Dependent Claim
19 words
The imager array of claim 18 , wherein the shape of the first portion is neither circular nor rectangular.
Claim 22
Dependent Claim
27 words
The imager array of claim 16 , wherein the N-well of each pixel acts as a lateral drain by preventing the charge from spreading to other pixels.
Claim 23
Dependent Claim
31 words
The imager array of claim 15 , wherein the charge held by the charge sensing second portion is cleared by biasing the second portion to the same potential as the substrate.
Claim 24
Dependent Claim
13 words
The imager array of claim 21 , wherein the potential is zero volts.
Claim 25
Dependent Claim
31 words
A pixel for an imager, comprising a charge collection gate formed in a semiconductor substrate; and a sense gate formed in the semiconductor substrate and substantially surrounding the charge collection gate.
Claim 26
Dependent Claim
31 words
A pixel for an imager, comprising a charge collection gate formed in a semiconductor substrate; and a sense gate formed in the semiconductor substrate and substantially surrounding the charge collection gate.
Claim 27
Dependent Claim
15 words
The pixel of claim 23 , the sense gate totally surrounds the charge collection gate.
Claim 28
Dependent Claim
25 words
The pixel of claim 23 , further comprising a lateral drain, the lateral drain providing a complete lateral block to charge transfer outside the pixel.
Claim 29
Dependent Claim
32 words
The pixel of claim 23 , the sense gate and charge collection gate formed so as to have a spaced-apart non-overlapping relationship with respect to the planar extension of the semiconductor substrate.
Claim 30
Dependent Claim
20 words
The pixel of claim 23 , further comprising a light blocking layer formed to block light to the sense gate.
Claim 31
Dependent Claim
23 words
The pixel of claim 23 , wherein the sense gate and the charge collection gate are formed from a single layer of material.
Claim 32
Dependent Claim
19 words
The pixel of claim 28 , wherein the single layer of material is a layer of CMOS compatible material.
Claim 33
Dependent Claim
14 words
The pixel of claim 29 , wherein the single layer of material is polysilicon.
Claim 34
Dependent Claim
16 words
The pixel of claim 27 , wherein the light blocking layer is formed of a metal.
Claim 35
Dependent Claim
19 words
The pixel of claim 25 , wherein the lateral drain is an N-well into which control FETs are formed.
Claim 36
Dependent Claim
26 words
The pixel of claim 29 , wherein the pixel is one of a matrix of identical pixels formed in the semiconductor substrate of an imager array.
References Cited (Backward Citations)
US5525813A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-14 | 2004-11-13 | 2005-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-14 | 2008-11-13 | 2009-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-14 | 2012-11-13 | 2013-05-15 | $7700.00 | Window Closed / Lapsed |