Digitally synthesized multiple phase pulse width modulation

Claim 2

A DC to DC power converter, comprising: an input for a source voltage; an output for a load voltage; at least one power conversion stage connected between said input and said output, said at least one power conversion stage having a control input for receiving a variable pulse width clock signal, said at least one power conversion stage producing a predetermined voltage at said output under control of said variable pulse width clock signal; and a controller having a feedback input connected to said output and a control output connected to said control input of said at least one power conversion stage, said controller having a digital circuit inducing a continuously variable phase shift between a reference clock signal and a relative clock signal dependent on an error signal generated from a difference between a signal at said feedback input and a reference signal.

Claim 3

A DC to DC power converter as claimed in claim 1 , wherein said controller includes a phase lock loop circuit connected to receive said reference clock signal and operable to generate said relative clock signal using said error signal to induce said phase shift.

Claim 4

A DC to DC power converter as claimed in claim 1 , wherein said at least one power conversion stage is a first power conversion stage, and further comprising: at least a second power conversion stage, said control output of said controller being a first control output and further comprising a second control output connected to said second power conversion stage.

Claim 5

A DC to DC power converter, comprising: an input for a source voltage; an output for a load voltage; at least one power conversion stage connected between said input and said output, said at least one power conversion stage having a control input for receiving a variable pulse width clock signal, said at least one power conversion stage producing a predetermined voltage at said output under control of said variable pulse width clock signal, said at least one power conversion stage including a plurality of power conversion stages; and a controller having a feedback input connected to said output and a control output connected to said control input of said at least one power conversion stage, said controller having a digital circuit inducing a phase shift between a reference clock signal and a relative clock signal dependent on an error signal generated from a difference between a signal at said feedback input and a reference signal, said controller including: an analog error signal portion connected to said output and to a predetermined reference voltage, said analog error signal portion generating an analog error signal corresponding to a difference between said load voltage and said predetermined reference voltage; a digital phase lock loop portion having a reference input and a relative input and an output, said digital phase lock loop portion connected to receive said analog error signal establish a phase shift between said reference input and said relative input; and a digital logic portion connected to receive a master reference clock signal, said digital logic portion including: a first divide by M circuit connected to receive said master reference clock signal, said first divide by M circuit generating a reference clock signal from said master reference clock signal, said reference clock signal being connected to said reference input of said digital phase lock loop portion, a second divide by M circuit connected to receive a master relative clock signal from said output of said digital phase lock loop portion, said second divide by M generating a relative clock signal that is fed to said relative input of said digital phase lock loop portion, logic circuits connected to receive said reference clock signal and said relative clock signal and conducting logic operations to generate control signals; and control outputs for the control signals corresponding in number to said plurality of power conversion stages.

Claim 6

A DC to DC power converter, comprising: an input for a source voltage; an output for a load voltage; at least one power conversion stage connected between said input and said output, said at least one power conversion stage having a control input for receiving a variable pulse width clock signal, said at least one power conversion stage producing a predetermined voltage at said output under control of said variable pulse width clock signal, said at least one power conversion stage including a plurality of power conversion stages; and a controller having a feedback input connected to said output and a control output connected to said control input of said at least one power conversion stage, said controller having a digital circuit inducing a phase shift between a reference clock signal and a relative clock signal dependent on an error signal generated from a difference between a signal at said feedback input and a reference signal, said controller including: an analog error signal portion connected to said output and to a predetermined reference voltage, said analog error signal portion generating an analog error signal corresponding to a difference between said load voltage and said predetermined reference voltage; a digital phase lock loop portion having a reference input and a relative input and an output, said digital phase lock loop portion connected to receive said analog error signal establish a phase shift between said reference input and said relative input; and a digital logic portion connected to receive a master reference clock signal, said digital logic portion including: a first divide by M circuit connected to receive said master reference clock signal, said first divide by M circuit generating a reference clock signal from said master reference clock signal, said reference clock signal being connected to said reference input of said digital phase lock loop portion, a second divide by M circuit connected to receive a master relative clock signal from said output of said digital phase lock loop portion, said second divide by M generating a relative clock signal that is fed to said relative input of said digital phase lock loop portion, logic circuits connected to receive said reference clock signal and said relative clock signal and conducting logic operations to generate control signals; and control outputs for the control signals corresponding in number to said plurality of power conversion stages.

Claim 7

A DC to DC power converter as claimed in claim 4 , wherein M of said first and second divide by M circuits is equivalent to number to said plurality of power conversion stages plus two.

Claim 10

A method as claimed in claim 6 , further comprising the step of: phase shifting said plurality of variable duty cycle clock signals with respect to each other.

Claim 13

A method as claimed in claim 8 , wherein said synthesizing step uses digital synthesis to convert said two phase-shifted frequency-matched clock signals to one or more variable duty cycle clock signals.

Claim 14

A method as claimed in claim 8 , wherein said synthesizing step uses digital synthesis to phase shift multiple variable duty cycle clocks signals.

Claim 15

A method as claimed in claim 8 , wherein said step of performing a single analog to digital conversion uses a modified phase lock loop for converting an error signal to two frequency matched clock signals of variable phase.

Claim 16

A method as claimed in claim 11 , further comprising the step of: detecting 0% and 100% limits defined for duty cycle while maintaining the modified phase lock loop in a lock condition.

Claim 17

A DC to DC power converter, comprising: an input for a source voltage; an output for a load voltage; a plurality of power conversion stages connected in parallel between said input and said output, said plurality of power conversion stages each having a control input for receiving a variable pulse width clock signal, said plurality of power conversion stages producing a predetermined voltage at said output under control of said variable pulse width clock signal; and a controller having: an analog error signal portion connected to said output and to a predetermined reference voltage, said analog error signal portion generating an analog error signal corresponding to a difference between said load voltage and said predetermined reference voltage; a digital phase lock loop portion having a reference input and a relative input and an output, said digital phase lock loop portion connected to receive said analog error signal and establish a phase shift between a reference signal at said reference input and a relative signal at said relative input dependent on said analog error signal; and a digital logic portion connected to receive a master reference clock signal, said digital logic portion including: a first divide by M circuit connected to receive said master reference clock signal, said first divide by M circuit generating a reference clock signal from said master reference clock signal, said reference clock signal being connected to said reference input of said digital phase lock loop portion, a second divide by M circuit connected to receive a master relative clock signal as an output signal from said output of said digital phase lock loop portion, said second divide by M generating a relative clock signal that is fed to said relative input of said digital phase lock loop portion, digital logic circuits receiving said reference and relative clock signals and generating control signals; and control outputs for said control signals corresponding in number to said plurality of power conversion stages.

Claim 18

A DC to DC power converter, comprising: an input for a source voltage; an output for a load voltage; a plurality of power conversion stages connected in parallel between said input and said output, said plurality of power conversion stages each having a control input for receiving a variable pulse width clock signal, said plurality of power conversion stages producing a predetermined voltage at said output under control of said variable pulse width clock signal; and a controller having: an analog error signal portion connected to said output and to a predetermined reference voltage, said analog error signal portion generating an analog error signal corresponding to a difference between said load voltage and said predetermined reference voltage; a digital phase lock loop portion having a reference input and a relative input and an output, said digital phase lock loop portion connected to receive said analog error signal and establish a phase shift between a reference signal at said reference input and a relative signal at said relative input dependent on said analog error signal; and a digital logic portion connected to receive a master reference clock signal, said digital logic portion including: a first divide by M circuit connected to receive said master reference clock signal, said first divide by M circuit generating a reference clock signal from said master reference clock signal, said reference clock signal being connected to said reference input of said digital phase lock loop portion, a second divide by M circuit connected to receive a master relative clock signal as an output signal from said output of said digital phase lock loop portion, said second divide by M generating a relative clock signal that is fed to said relative input of said digital phase lock loop portion, digital logic circuits receiving said reference and relative clock signals and generating control signals; and control outputs for said control signals corresponding in number to said plurality of power conversion stages.