Phase control circuit, semiconductor device and semiconductor memory

Claim 2

A phase control circuit, comprising: a plurality of fixed delay circuits which respectively receive a first clock signal therein and add predetermined delay times different from one another to the input first clock signal; a detection circuit which receives clock signals outputted from said plurality of fixed delay circuits and a second clock signal different in phase from the first clock signal therein and generates detected signals represented in a plurality of bits each corresponding to the difference in phase between the second clock signal and the first clock signal; and a variable delay circuit which receives the detected signals represented in a plurality of bits outputted from said detection circuit in parallel therein and gives a delay in the phase difference corresponding to said each input detected signal to a third clock signal.

Claim 3

The phase control circuit according to claim 1 , wherein said fixed delay circuits and said variable delay circuit respectively comprise current control type inverters whose operating currents are determined according to switched states of current source transistors, and said variable delay circuit includes the current source transistors in parallel in plural form, said plurality of current source transistors being respectively switch-controlled according to the detected signals represented in the plurality of bits.

Claim 4

The phase control circuit according to claim 1 , wherein said fixed delay circuits and said variable delay circuit respectively include capacitive elements provided within signal transfer paths through switch transistors and said variable delay circuit includes the capacitive elements and switch transistors in parallel in plural form, said plurality of switch transistors being respectively switch-controlled based on the detected signals represented in the plurality of bits.

Claim 5

The phase control circuit according to claim 3 , further including a latch circuit which latches the detected signals for each period greater than one cycle of the second clock signal and supplies the same to said variable delay circuit.

Claim 6

The phase control circuit according to claim 4 , wherein said first clock signal is a clock signal obtained by adding first and second delay times to the second clock signal, said third clock signal is a clock signal obtained by adding the second delay time to the second clock signal.

Claim 7

A semiconductor device, comprising: a semiconductor chip including, a clock terminal which receives an external clock signal therein; a clock input circuit connected to said clock terminal; a phase control circuit according to any of claims 1 to 5 , which is connected to said clock input circuit; a data output circuit connected to said phase control circuit; and data terminals which are connected to said data output circuit and used to output data to the outside, and wherein the third clock signal is a clock signal delayed a predetermined time with respect to the external clock signal, and said data output circuit is a circuit which outputs the data in phase with the external clock signal in synchronism with the signal outputted from the variable delay circuit in said phase control circuit.

Claim 8

The semiconductor device according to claim 6 , wherein said data output circuit is a circuit capable of outputting a data strobe signal in phase with the external clock signal in synchronism with the signal outputted from the variable delay circuit in said phase control circuit.

Claim 9

A semiconductor device, comprising: a clock input circuit which receives an external clock signal therein to thereby generate an internal clock signal; an internal circuit activated in synchronism with the internal clock signal; an output circuit which outputs the result of operation of said internal circuit to the outside; and a clock reproducing circuit for matching the phase of output operation by said output circuit with that of the external clock signal, said clock reproducing circuit including, first and second predetermined delay circuits which respectively add predetermined delay times to a reference clock signal synchronized with the internal clock signal and are connected to each other in series form; a phase difference detection circuit which detects the difference in phase between the output of said second predetermined delay circuit and the reference clock signal; a first phase difference reproduction circuit which adds the phase difference detected by said phase difference detection circuit to an output clock signal of said first predetermined delay circuit; a plurality of fixed delay circuits which respectively receive a first clock signal outputted from said first phase difference reproduction circuit therein and add predetermined delay times different from one another to the input first clock signal; a detection circuit which receives clock signals outputted from said plurality of fixed delay circuits and the reference clock signal therein and generates detected signals represented in plural bits each corresponding to the difference in phase between the reference clock signal and the first clock signal; a second phase difference reproduction circuit which adds the phase difference detected by said phase difference detection circuit to the reference clock signal; and a variable delay circuit which receives said detected signals represented in a plurality of bits in parallel from said detection circuit and adds a delay in the phase difference corresponding to said each input detected signal to a clock signal outputted from said second phase difference reproduction circuit; and wherein said output circuit allows the phase of the output operation to coincide with that of the external clock signal in synchronism with a clock signal outputted from said variable delay circuit.

Claim 10

A semiconductor device, comprising: a clock input circuit which receives an external clock signal therein to thereby generate an internal clock signal; an internal circuit activated in synchronism with the internal clock signal; an output circuit which outputs the result of operation of said internal circuit to the outside; and a clock reproducing circuit for matching the phase of output operation by said output circuit with that of the external clock signal, said clock reproducing circuit including, first and second predetermined delay circuits which respectively add predetermined delay times to a reference clock signal synchronized with the internal clock signal and are connected to each other in series form; a phase difference detection circuit which detects the difference in phase between the output of said second predetermined delay circuit and the reference clock signal; a first phase difference reproduction circuit which adds the phase difference detected by said phase difference detection circuit to an output clock signal of said first predetermined delay circuit; a plurality of fixed delay circuits which respectively receive a first clock signal outputted from said first phase difference reproduction circuit therein and add predetermined delay times different from one another to the input first clock signal; a detection circuit which receives clock signals outputted from said plurality of fixed delay circuits and the reference clock signal therein and generates detected signals represented in plural bits each corresponding to the difference in phase between the reference clock signal and the first clock signal; a second phase difference reproduction circuit which adds the phase difference detected by said phase difference detection circuit to the reference clock signal; and a variable delay circuit which receives said detected signals represented in a plurality of bits in parallel from said detection circuit and adds a delay in the phase difference corresponding to said each input detected signal to a clock signal outputted from said second phase difference reproduction circuit; and wherein said output circuit allows the phase of the output operation to coincide with that of the external clock signal in synchronism with a clock signal outputted from said variable delay circuit.

Claim 11

The semiconductor device according to claim 8 , wherein said first predetermined delay circuit has a signal propagation delay time corresponding to a delay time equal to the sum of an operation delay time during which said clock input circuit generates the internal clock signal from the external clock signal and generates the reference clock signal from the internal clock signal, and an operation delay time during which the output clock signal of said variable delay circuit is inputted to allow said output circuit to perform the output operation.

Claim 12

The semiconductor device according to claim 9 , wherein said second predetermined delay circuit has a delay time smaller than the maximum control width of a delay time capable of being supplied from said variable delay circuit.

Claim 13

The semiconductor device according to claim 10 , wherein said phase difference detection circuit is a forward delay circuit for successively propagating the output of said second predetermined delay circuit, which has a plurality of unit delay circuits provided in series form and selects the position of an output of said each unit delay circuit, which most approximates the state of the reference clock signal, said first phase difference reproduction circuit is a first backward delay circuit which has a plurality of unit delay circuits provided in series form in the reverse direction, each having a delay characteristic identical to or substantially identical to that of said forward delay circuit and which selects an input position of each of the unit delay circuits having, at a subsequent stage, the same number of stages as the number of stages of the unit delay circuits each corresponding to the output position selected by said forward delay circuit and adds the output of said first predetermined delay circuit to the selected input position, and said second phase difference reproduction circuit is a second backward delay circuit which has a plurality of unit delay circuits provided in series form in the reverse direction, each having a delay characteristic identical to or substantially identical to that of said forward delay circuit and which selects an input position of each of the unit delay circuits having, at a subsequent stage, the same number of stages as the number of stages of the unit delay circuits each corresponding to the output position selected by said forward delay circuit and adds the reference clock signal to the selected input position.

Claim 14

The semiconductor device according to claim 11 , wherein said fixed delay circuits and said variable delay circuit respectively comprise current control type inverters whose operating currents are determined according to switched states of current source transistors, and said variable delay circuit includes the current source transistors in parallel in plural form, said plurality of current source transistors being respectively switch-controlled according to the detected signals represented in the plural bits.

Claim 15

The semiconductor device according to claim 11 , wherein said fixed delay circuits and said variable delay circuit respectively include capacitive elements provided within signal transfer paths through switch transistors and said variable delay circuit includes the capacitive elements and switch transistors in parallel in plural form, said plurality of switch transistors being respectively switch-controlled based on the detected signals represented in the plurality of bits.

Claim 16

The semiconductor device according to claim 8 , further including a first latch circuit which latches the phase difference detected by said phase difference detection circuit for each period greater than one cycle of the second clock signal and supplies the same to said second phase difference reproduction circuit, and a second latch circuit which latches the detected signals outputted from said detection circuit in synchronism with the latch operation of said first latch circuit and supplies the same to said variable delay circuit.

Claim 17

The semiconductor device according to claim 8 , wherein said output circuit is a circuit capable of outputting a data strobe signal in phase with the external clock signal in synchronism with a signal outputted from said variable delay circuit in said clock reproducing circuit.

Claim 18

A signal generating circuit, comprising: a control circuit which compares each of a plurality of signals different in change timing from one another with a signal in a predetermined cycle of a reference clock signal to thereby output a detected signal; and an output circuit which outputs a signal corresponding to the reference clock signal, based on the detected signal; and a plurality of delay circuits respectively provided with delay time control units, and wherein each individuals of said plurality of delay circuits are first delay circuits provided within said output circuit, said plurality of other delay circuits excluding said plurality of first delay circuits are a plurality of second delay circuits provided within said control circuit, said plurality of second delay circuits respectively output said plurality of signals different in change timing from one another in response to a common input signal, and each of delay control units of said first delay circuits is variably controlled based on the detected signal.

Claim 19

A signal generating circuit, comprising: a control circuit which compares each of a plurality of signals different in change timing from one another with a signal in a predetermined cycle of a reference clock signal to thereby output a detected signal; and an output circuit which outputs a signal corresponding to the reference clock signal, based on the detected signal; and a plurality of delay circuits respectively provided with delay time control units, and wherein each individuals of said plurality of delay circuits are first delay circuits provided within said output circuit, said plurality of other delay circuits excluding said plurality of first delay circuits are a plurality of second delay circuits provided within said control circuit, said plurality of second delay circuits respectively output said plurality of signals different in change timing from one another in response to a common input signal, and each of delay control units of said first delay circuits is variably controlled based on the detected signal.

Claim 20

The signal generating circuit according to claim 16 , which is included in a semiconductor device, and wherein said semiconductor device includes a clock terminal which receives an external clock signal from outside said semiconductor device, data terminals which output data to the outside of said semiconductor device, and a data output circuit connected to the data terminals, said reference clock signal is a signal corresponding to the external clock signal, and said data output circuit responds to the signal outputted from said output circuit of said signal generating circuit and outputs the data with timing synchronized with the external clock signal.

Claim 21

The signal generating circuit according to claim 16 , wherein said plurality of delay circuits further include main delay units respectively, and delay times of said respective delay circuits are respectively set by said main delay units and said delay control units.