US6204728B1
Expired / Lapsed
US
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Radio frequency amplifier with reduced intermodulation distortion
Assignee: Maxim Integrated Products Inc
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Filing: 1999-01-28
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Granted: 2001-03-20
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Expires: 2019-01-28
Abstract
Abstract Apparatus and methods of broadband amplification with high linearity and low power consumption are described. An apparatus configured to amplify a signal includes an input transistor and an output transistor coupled together in a cascode configuration with the input transistor defining an input of the amplifier and the output transistor defining an output of the amplifier. A feedback network is coupled between the input and the output and is characterized by an impedance of substantially zero resistance and non-zero reactance. A method of amplifying a signal is also described. An input signal is received at an input; the input signal is amplified to provide an output signal at an output; and the output signal is sampled at the input through a feedback network characterized by an impedance of substantially zero resistance and ion-zero reactance. A method of making an apparatus configured to amplify a signal is also described.
Inventors
- 👤 Johannes J. E. M. Hageraats
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:38
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/34; H03F1/08; H03F1/22; H03F2201/00; H03F2201/32; H03F2201/3215
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
92 words
An apparatus configured to amplify a signal, comprising: an input transistor and an output transistor coupled together in a cascode configuration, wherein the input transistor is configured to receive a radio frequency signal; a shunt capacitive feedback network coupled between the input transistor and the output transistor and characterized by an impedance of substantially zero resistance and non-zero reactance, wherein the reactance is selected to reduce third-order intermodulation distortion products at the output transistor; and a series inductive feedback network coupled between the emitter of the input transistor and a reference point.
Claim 2
Independent Claim
92 words
An apparatus configured to amplify a signal, comprising: an input transistor and an output transistor coupled together in a cascode configuration, wherein the input transistor is configured to receive a radio frequency signal; a shunt capacitive feedback network coupled between the input transistor and the output transistor and characterized by an impedance of substantially zero resistance and non-zero reactance, wherein the reactance is selected to reduce third-order intermodulation distortion products at the output transistor; and a series inductive feedback network coupled between the emitter of the input transistor and a reference point.
Claim 3
Dependent Claim
16 words
The apparatus of claim 1 , wherein the shunt capacitive feedback network comprises a feedback capacitor.
Claim 4
Dependent Claim
17 words
The apparatus of claim 1 , wherein the shunt capacitive feedback network consists essentially of capacitive reactance.
Claim 5
Dependent Claim
30 words
The apparatus of claim 1 , wherein the series inductive and shunt capacitive feedback networks have respective reactance's selected to achieve a desired impedance at the input of the apparatus.
Claim 6
Dependent Claim
42 words
The apparatus of claim 1 , wherein the reactance of the combined series inductive and shunt capacitive feedback networks is selected to achieve an impedance at the input of the apparatus that is substantially independent of frequency over a broad frequency range.
Claim 7
Dependent Claim
23 words
The apparatus of claim 1 , configured to amplify a signal having a frequency of at least about 500 MHZ with substantial linearity.
Claim 8
Dependent Claim
49 words
The apparatus of claim 1 , further comprising a receiver input coupled to the apparatus input and configured to receive a wireless signal, and a receiver output coupled to the apparatus output and configured to produce an output signal representative of the wireless signal received at the receiver input.
Claim 9
Independent Claim
100 words
A method of amplifying a signal, comprising: receiving an input radio frequency signal at the base of an input transistor coupled to an output transistor in a cascode configuration, the input transistor having an emitter degeneratively coupled to a reference point through a series inductive circuit; amplifying the input signal to provide an output signal at the collector of the output transistor; and rejecting third order intermodulation distortion products at the output transistor by feeding the output signal back to the input transistor through a shunt capacitive feedback network characterized by an impedance of substantially zero resistance and non-zero reactance.
Claim 10
Independent Claim
100 words
A method of amplifying a signal, comprising: receiving an input radio frequency signal at the base of an input transistor coupled to an output transistor in a cascode configuration, the input transistor having an emitter degeneratively coupled to a reference point through a series inductive circuit; amplifying the input signal to provide an output signal at the collector of the output transistor; and rejecting third order intermodulation distortion products at the output transistor by feeding the output signal back to the input transistor through a shunt capacitive feedback network characterized by an impedance of substantially zero resistance and non-zero reactance.
Claim 11
Dependent Claim
45 words
The method of claim 8 , wherein the output signal is fed back to the base of the input transistor by coupling the collector of the output transistor to the base of the input transistor through a feedback network that consists essentially of capacitive reactance.
Claim 12
Dependent Claim
25 words
The method of claim 8 , further comprising selecting the reactances of the series inductive and shunt capacitive feedback circuits to match an output impedance.
Claim 13
Independent Claim
147 words
An apparatus configured to amplify a signal, comprising: first and second amplification stages, wherein each amplification stage comprises an input transistor and an output transistor coupled together in a cascode configuration with the base of the input transistor defining an input of the amplification stage and the collector of the output transistor defining an output of the amplification stage, a shunt capacitive feedback network coupled between the input and the output and characterized by an impedance of substantially zero resistance and non-zero reactance the network configured to reject third order intermodulation distortion products and a series inductive feedback network coupled between the base of the input transistor and a reference point and consisting essentially of inductive reactance; wherein the inputs of the amplification stages are coupled together to form an input of the apparatus, and the outputs of the amplification stages are coupled together by an isolator.
Claim 14
Independent Claim
147 words
An apparatus configured to amplify a signal, comprising: first and second amplification stages, wherein each amplification stage comprises an input transistor and an output transistor coupled together in a cascode configuration with the base of the input transistor defining an input of the amplification stage and the collector of the output transistor defining an output of the amplification stage, a shunt capacitive feedback network coupled between the input and the output and characterized by an impedance of substantially zero resistance and non-zero reactance the network configured to reject third order intermodulation distortion products and a series inductive feedback network coupled between the base of the input transistor and a reference point and consisting essentially of inductive reactance; wherein the inputs of the amplification stages are coupled together to form an input of the apparatus, and the outputs of the amplification stages are coupled together by an isolator.
Claim 15
Dependent Claim
12 words
The apparatus of claim 11 , wherein the isolator comprises a diode.
References Cited (Backward Citations)
US3371283A
Cited
US4406990A
Cited
US4511857A
Cited
US4523057A
Cited
US4706038A
Cited
US5157345A
Cited
US5334946A
Cited
US5015968A
Cited
US5319318A
Cited
US5157351A
Cited
US5276406A
Cited
US5481389A
Cited
US5491450A
Cited
US5426641A
Cited
US5451906A
Cited
US5661437A
Cited
US5732341A
Cited
US5646573A
Cited
US5945880A
Cited
FR2762727A1
Cited
US6054880A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-19 | 2004-09-18 | 2005-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-19 | 2008-09-18 | 2009-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-19 | 2012-09-18 | 2013-03-20 | $7700.00 | Window Closed / Lapsed |