Patent US6201296B1 successfully refreshed from Google Patents.
US6201296B1
Expired / Lapsed
US
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Semiconductor chip with protection against analyzing
Assignee: Siemens AG
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Filing: 1999-03-23
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Granted: 2001-03-13
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Expires: 2019-03-23
Abstract
Abstract A copy-protection device for a semiconductor chip with a cover has a resonant oscillating circuit whose elements are located on the chip surface and within the cover. The semiconductor chip also has an evaluation circuit connected to the oscillating circuit. The evaluation circuit disables the semiconductor chip if the oscillating circuit is detuned and thus stopped from resonating. This detuning of the oscillating circuit occurs when the cover is removed, since the cover acts as a dielectric for the capacitor. After the cover has been removed, it is impossible to operate the semiconductor chip, in order to copy or analyze it.
Inventors
- 👤 Manfred Fries
- 👤 Peter Stampka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:22
CPC Classifications
H; H10; H10W; H10W42/00; H10W42/40; H10W42/405; G; G06; G06F; G06F21/00; G06F21/70; G06F21/86; Y; Y10; Y10S; Y10S257/00; Y10S257/922
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
83 words
A semiconductor device, comprising: a semiconductor chip having a coil and a capacitor defining an oscillating circuit with a resonant frequency; an electrically insulating layer forming a dielectric for said capacitor and covering said semiconductor chip; and an evaluation circuit connected to said oscillating circuit for detecting a detuning of said oscillating circuit due to a change in said resonant frequency caused by altering said electrically insulating layer, said evaluation circuit disabling said semiconductor chip upon detecting the detuning of said oscillating circuit.
Claim 2
Dependent Claim
83 words
A semiconductor device, comprising: a semiconductor chip having a coil and a capacitor defining an oscillating circuit with a resonant frequency; an electrically insulating layer forming a dielectric for said capacitor and covering said semiconductor chip; and an evaluation circuit connected to said oscillating circuit for detecting a detuning of said oscillating circuit due to a change in said resonant frequency caused by altering said electrically insulating layer, said evaluation circuit disabling said semiconductor chip upon detecting the detuning of said oscillating circuit.
Claim 3
Dependent Claim
31 words
The semiconductor device according to claim 1 , wherein said semiconductor chip has a top surface, at least said coil being formed as a metallic conductor track over said top surface.
Claim 4
Dependent Claim
28 words
The semiconductor device according to claim 2 , wherein said metallic conductor track includes parallel conductor track sections, said capacitor being formed by said parallel conductor track sections.
Claim 5
Dependent Claim
24 words
The semiconductor device according to claim 1 , which further comprises at least a further oscillating circuit coupled to said oscillating circuit for oscillating.
Claim 6
Dependent Claim
22 words
The semiconductor device according to claim 1 , wherein said semiconductor chip has a surface, said coil spanning said surface substantially entirely.
Claim 7
Dependent Claim
22 words
The semiconductor device according to claim 2 , wherein said capacitor substantially entirely occupies said top surface at free surface areas thereof.
Claim 8
Dependent Claim
39 words
The semiconductor device according to claim 1 , wherein said evaluation circuit, after application of said electrically insulating layer, ascertains said resonant frequency of said oscillating circuit and drives said oscillating circuit during an operation of said semiconductor chip.
Claim 9
Dependent Claim
20 words
The semiconductor device according to claim 1 , wherein said evaluation circuit drives said oscillating circuit at a preset frequency.
Claim 10
Dependent Claim
37 words
The semiconductor device according to claim 1 , wherein said electrically insulating layer forms a cover for said semiconductor chip, said evaluation circuit detecting the detuning of said oscillating circuit due to a removal of said cover.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-12 | 2004-09-11 | 2005-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-12 | 2008-09-11 | 2009-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-12 | 2012-09-11 | 2013-03-13 | $7700.00 | Window Closed / Lapsed |