US6199183B1
Expired / Lapsed
US
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Method of forming a scan path network
Assignee: Oki Electric Industry Co Ltd
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Filing: 1998-06-04
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Granted: 2001-03-06
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Expires: 2018-06-04
Abstract
Abstract In a method of forming a scan path network, typical of the present invention, at a semiconductor integrated circuit having a clock node supplying a clock signal, a scan-in node supplying scan data and a scan-out node for receiving scan data outputted from scan flip-flops, the following steps are carried out. A plurality of scan flip-flops are placed. Delay times taken for the clock signal supplied to the clock node to reach the scan flip-flops are calculated. Distances between the scan flip-flops are calculated. Skews between the scan flip-flops are calculated. A sum of the calculated distances and the skews is calculated. The smallest value from within this total is then decided upon. The scan flip-flops are then connected across the scan-in node and the scan-out node based on this smallest value.
Inventors
- 👤 Mitsuru Nadaoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/318577; G01R31/31858
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
133 words
A method of forming a scan path network at a semiconductor integrated circuit having a clock node supplied with a clock signal, a scan-in node supplied with scan data and a scan-out node for receiving scan data outputted from scan flip-flops, said method comprising the steps of: (a) arranging a plurality of scan flip-flops, (b) calculating delay times for said clock signal supplied to said clock node to reach said scan flip-flops, (c) calculating distances between said scan flip-flops, (d) calculating skews between said scan flip-flops, (e) calculating a sum of said calculated distances and said skews, (f) deciding upon the smallest value of calculation results of said step (e), and (g) connecting said scan flip-flops between said scan-in node and said scan-out node based on the value obtained in said step (f).
Claim 2
Independent Claim
133 words
A method of forming a scan path network at a semiconductor integrated circuit having a clock node supplied with a clock signal, a scan-in node supplied with scan data and a scan-out node for receiving scan data outputted from scan flip-flops, said method comprising the steps of: (a) arranging a plurality of scan flip-flops, (b) calculating delay times for said clock signal supplied to said clock node to reach said scan flip-flops, (c) calculating distances between said scan flip-flops, (d) calculating skews between said scan flip-flops, (e) calculating a sum of said calculated distances and said skews, (f) deciding upon the smallest value of calculation results of said step (e), and (g) connecting said scan flip-flops between said scan-in node and said scan-out node based on the value obtained in said step (f).
Claim 3
Dependent Claim
18 words
The method of claim 1 , wherein said step (b) and said step (c) are executed in parallel.
Claim 4
Dependent Claim
26 words
The method of claim 1 , wherein said step (b) defines a plurality of groups comprised of pluralities of scan flip-flops having substantially equal delay times.
Claim 5
Dependent Claim
21 words
The method of claim 3 , wherein a logic circuit is connected across said clock node and one of said groups.
Claim 6
Dependent Claim
14 words
The method of claim 4 , wherein said logic circuit is an AND gate.
Claim 7
Dependent Claim
40 words
The method of claim 4 , wherein a period of a clock signal supplied to one of said groups of flip-flops and a period of a clock signal supplied to a further group of said groups of flip-flops are different.
Claim 8
Dependent Claim
40 words
The method of claim 1 , further comprising the steps of: after said step (f), calculating whether or not skews between said flip-flops exceed a reference value, and inserting delay means between said flip-flops having skews exceeding said reference value.
Claim 9
Dependent Claim
13 words
The method of claim 7 , wherein said delay means is a buffer.
Claim 10
Independent Claim
156 words
A method of forming a scan path network at a semiconductor integrated circuit having a clock node supplied with a clock signal, a scan-in node supplied with scan data and a scan-out node for receiving scan data outputted from scan flip-flops, said method comprising the steps of: (a) arranging a plurality of scan flip-flops, (b) calculating delay times for said clock signal supplied to said clock node to reach said scan flip-flops, (c) calculating distances between said scan flip-flops, (d) calculating skews between said scan flip-flops, (e) calculating a sum of said calculated distances, (f) deciding upon the smallest value of calculation results of said step (c), (g) calculating whether or not skews between said flip-flops exceed a reference value, (h) inserting delay means between said flip-flops having skews exceeding said reference value, and (i) connecting said scan flip-flops between said scan-in node and said scan-out node based on the value obtained in said step (f).
Claim 11
Independent Claim
156 words
A method of forming a scan path network at a semiconductor integrated circuit having a clock node supplied with a clock signal, a scan-in node supplied with scan data and a scan-out node for receiving scan data outputted from scan flip-flops, said method comprising the steps of: (a) arranging a plurality of scan flip-flops, (b) calculating delay times for said clock signal supplied to said clock node to reach said scan flip-flops, (c) calculating distances between said scan flip-flops, (d) calculating skews between said scan flip-flops, (e) calculating a sum of said calculated distances, (f) deciding upon the smallest value of calculation results of said step (c), (g) calculating whether or not skews between said flip-flops exceed a reference value, (h) inserting delay means between said flip-flops having skews exceeding said reference value, and (i) connecting said scan flip-flops between said scan-in node and said scan-out node based on the value obtained in said step (f).
Claim 12
Dependent Claim
13 words
The method of claim 9 , wherein said delay means is a buffer.
Claim 13
Dependent Claim
18 words
The method of claim 9 , wherein said step (b) and said step (c) are executed in parallel.
Claim 14
Dependent Claim
26 words
The method of claim 9 , wherein said step (b) defines a plurality of groups comprised of pluralities of scan flip-flops having substantially equal delay times.
Claim 15
Dependent Claim
21 words
The method of claim 12 , wherein a logic circuit is connected across said clock node and one of said groups.
Claim 16
Dependent Claim
14 words
The method of claim 13 , wherein said logic circuit is an AND gate.
Claim 17
Dependent Claim
41 words
The method of claim 13 , wherein a period of a clock signal supplied to one group of said groups of flip-flops and a period of a clock signal supplied to a further group of said groups of flip-flops are different.
Claim 18
Independent Claim
220 words
A method of forming a scan path network at a semiconductor integrated circuit having a clock node supplied with a clock signal, a scan-in node supplied with scan data and a scan-out node for receiving scan data outputted from scan flip-flops, said method comprising the steps of: (a) arranging a plurality of first scan flip-flops operating in synchronization with a rising edge of said clock signal and a plurality of second scan flip-flops operating in synchronization with a falling edge of said clock signal, (b) calculating delay times for said clock signal supplied to said clock node to reach said scan flip-flops, (c) calculating distances between said first scan flip-flops and calculating distances between said second scan flip-flops, (d) calculating skew between said first scan flip-flops and calculating skew between said second scan flip-flops, (e) calculating a total of said distances and said skews relating to said first scan flip-flops and calculating a total of said distances and said skews relating to said second scan flip-flops, (f) deciding upon a minimum value relating to said first scan flip-flops and deciding upon a minimum value relating to said second scan flip-flops from calculation results of said step (e), and (g) connecting said scan flip-flops between said scan-in node and said scan-out node based on the value obtained in said step (f).
Claim 19
Independent Claim
220 words
A method of forming a scan path network at a semiconductor integrated circuit having a clock node supplied with a clock signal, a scan-in node supplied with scan data and a scan-out node for receiving scan data outputted from scan flip-flops, said method comprising the steps of: (a) arranging a plurality of first scan flip-flops operating in synchronization with a rising edge of said clock signal and a plurality of second scan flip-flops operating in synchronization with a falling edge of said clock signal, (b) calculating delay times for said clock signal supplied to said clock node to reach said scan flip-flops, (c) calculating distances between said first scan flip-flops and calculating distances between said second scan flip-flops, (d) calculating skew between said first scan flip-flops and calculating skew between said second scan flip-flops, (e) calculating a total of said distances and said skews relating to said first scan flip-flops and calculating a total of said distances and said skews relating to said second scan flip-flops, (f) deciding upon a minimum value relating to said first scan flip-flops and deciding upon a minimum value relating to said second scan flip-flops from calculation results of said step (e), and (g) connecting said scan flip-flops between said scan-in node and said scan-out node based on the value obtained in said step (f).
Claim 20
Dependent Claim
18 words
The method of claim 16 , wherein said step (b) and said step (c) are executed in parallel.
Claim 21
Dependent Claim
21 words
The method of claim 16 , wherein a logic circuit is connected actors said clock node and one of said groups.
Claim 22
Dependent Claim
14 words
The method of claim 18 , wherein said logic circuit is an AND gate.
Claim 23
Dependent Claim
34 words
The method of claim 18 , wherein a period of a clock signal supplied to said first scan flip-flops and a period of a clock signal supplied to said second scan flip-flops are different.
Claim 24
Dependent Claim
40 words
The method of claim 16 , further comprising the steps of: after said step (f), calculating whether or not skews between said flip-flops exceed a reference value, and inserting delay means between said flip-flops having skews exceeding said reference value.
Claim 25
Dependent Claim
13 words
The method of claim 21 , wherein said delay means is a buffer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-05 | 2004-09-04 | 2005-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-05 | 2008-09-04 | 2009-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-05 | 2012-09-04 | 2013-03-06 | $7700.00 | Window Closed / Lapsed |