Device for generating error path list and method of extracting the worst paths

Claim 1

A device for generating an error path list for analyzing delay times of paths generating errors, said paths connecting first nodes with second nodes, said device comprising: reading means for reading information on said paths and said delay times thereof; representative-path extraction means using said information for extracting from said paths representative paths which are worst in terms of said delay times, said representative-path extraction means comprising; first means for determining a worst error path for a given one of said second nodes by selecting a path having the longest delay time among said paths connected to said given one of said second nodes, said first means selecting said worst error path for each of said second nodes; and second means for determining a representative path for a given one of said first nodes by selecting said worst error path having the longest delay time among more than one worst error path connected to said given one of said first nodes if more than one worst error path is connected to said given one of said first nodes, and by selecting said worst error path connected to said given one of said first nodes as said representative path if only one worst error path is connected to said given one of said first nodes, said representative path for all of said first nodes being said representative paths; and output means for generating said error path list reporting said representative paths.

Claim 2

A device for generating an error path list for analyzing delay times of paths generating errors, said paths connecting first nodes with second nodes, said device comprising: reading means for reading information on said paths and said delay times thereof; representative-path extraction means using said information for extracting from said paths representative paths which are worst in terms of said delay times, said representative-path extraction means comprising; first means for determining a worst error path for a given one of said second nodes by selecting a path having the longest delay time among said paths connected to said given one of said second nodes, said first means selecting said worst error path for each of said second nodes; and second means for determining a representative path for a given one of said first nodes by selecting said worst error path having the longest delay time among more than one worst error path connected to said given one of said first nodes if more than one worst error path is connected to said given one of said first nodes, and by selecting said worst error path connected to said given one of said first nodes as said representative path if only one worst error path is connected to said given one of said first nodes, said representative path for all of said first nodes being said representative paths; and output means for generating said error path list reporting said representative paths.

Claim 10

A method of extracting representative paths which are worst in terms of delay times among paths generating errors, said paths connecting first nodes with second nodes, said method comprising: a) receiving information on said paths and said delay times thereof; b) determining a worst error math for a given one of said second nodes by selecting a path having the longest delay time among said paths connected to said given one of said second nodes, said worst error path being selected for each of said second nodes; and c) determining a representative path for a given one of said first nodes by selecting said worst error path having the longest delay time among more than one worst error path connected to said given one of said first nodes if more than one worst error path is connected to said given one of said first nodes, and by selecting said worst error path connected to said given one of said first nodes as said representative oath if only one worst error path is connected to said given one of said first nodes, said representative path for all of said first nodes being said representative paths.

Claim 11

A method of extracting representative paths which are worst in terms of delay times among paths generating errors, said paths connecting first nodes with second nodes, said method comprising: a) receiving information on said paths and said delay times thereof; b) determining a worst error math for a given one of said second nodes by selecting a path having the longest delay time among said paths connected to said given one of said second nodes, said worst error path being selected for each of said second nodes; and c) determining a representative path for a given one of said first nodes by selecting said worst error path having the longest delay time among more than one worst error path connected to said given one of said first nodes if more than one worst error path is connected to said given one of said first nodes, and by selecting said worst error path connected to said given one of said first nodes as said representative oath if only one worst error path is connected to said given one of said first nodes, said representative path for all of said first nodes being said representative paths.

Claim 13

A method for performing delay time analysis of a logic circuit, comprising: (a) grouping nodes of the logic circuit into a plurality of node groups; (b) selecting a representative path for each possible pair of node groups using path delay times between the nodes to determine a worst delay path; (c) selecting a source node group and a target node group from the node groups; and (d) determining a representative path between said source node group and said target node group by, (d1) determining a first worst delay path by finding a longest delay path from a source pin to each source node of said source node group, (d2) determining a second worst delay path by finding a longest delay path from a target pin to each target node of said target node group, and (d3) determining said representative path by concatenating the first worst delay path and second worst delay path.

Claim 14

A method for performing delay time analysis of a logic circuit, comprising: (a) grouping nodes of the logic circuit into a plurality of node groups; (b) selecting a representative path for each possible pair of node groups using path delay times between the nodes to determine a worst delay path; (c) selecting a source node group and a target node group from the node groups; and (d) determining a representative path between said source node group and said target node group by, (d1) determining a first worst delay path by finding a longest delay path from a source pin to each source node of said source node group, (d2) determining a second worst delay path by finding a longest delay path from a target pin to each target node of said target node group, and (d3) determining said representative path by concatenating the first worst delay path and second worst delay path.